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20 TSSOP
Integrated Circuits (ICs)

SN74LVTH273MNSREP

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Texas Instruments

ENHANCED PRODUCT 3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

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20 TSSOP
Integrated Circuits (ICs)

SN74LVTH273MNSREP

Active
Texas Instruments

ENHANCED PRODUCT 3.3-V ABT OCTAL D-TYPE FLIP-FLOPS WITH CLEAR

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVTH273MNSREP
Clock Frequency150 MHz
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Current - Quiescent (Iq)190 çA
Input Capacitance4 pF
Max Propagation Delay @ V, Max CL4.9 ns
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Output TypeNon-Inverted
Package / Case20-SOIC
Package / Case0.209 "
Package / Case5.3 mm
Supplier Device Package20-SO
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]2.7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 3.30
Digi-Reel® 1$ 3.30
Tape & Reel (TR) 2000$ 2.04
4000$ 1.99
6000$ 1.67
Texas InstrumentsLARGE T&R 1$ 2.99
100$ 2.62
250$ 1.84
1000$ 1.48

Description

General part information

SN74LVTH273-EP Series

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.