SN74LVTH273-EP Series

Enhanced Product 3.3-V Abt Octal D-Type Flip-Flops With Clear

Catalog

Enhanced Product 3.3-V Abt Octal D-Type Flip-Flops With Clear

Part	Input Capacitance	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Bits per Element	Operating Temperature [Max]	Operating Temperature [Min]	Clock Frequency	Type	Current - Quiescent (Iq)	Output Type	Number of Elements	Max Propagation Delay @ V, Max CL	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Mounting Type	Package / Case	Package / Case [y]	Package / Case [y]	Trigger Type	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case	Package / Case [x]
Texas Instruments SN74LVTH273DWRE4	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-SOIC	Surface Mount	20-SOIC	0.295 in	7.5 mm	Positive Edge
Texas Instruments SN74LVTH273DWRG4	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-SOIC	Surface Mount	20-SOIC	0.295 in	7.5 mm	Positive Edge
Texas Instruments SN74LVTH273MNSREP	4 pF	64 mA	32 mA	8			150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-SO	Surface Mount	20-SOIC			Positive Edge	125 °C	-55 °C	0.209 "	5.3 mm
Texas Instruments SN74LVTH273PW	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-TSSOP	Surface Mount	20-TSSOP	4.4 mm		Positive Edge					0.173 in
Texas Instruments SN74LVTH273PWR	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-TSSOP	Surface Mount	20-TSSOP	4.4 mm		Positive Edge					0.173 in
Texas Instruments SN74LVTH273IPWREP	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-TSSOP	Surface Mount	20-TSSOP	4.4 mm		Positive Edge					0.173 in
Texas Instruments SN74LVTH273NSR	4 pF	64 mA	32 mA	8	85 °C	-40 °C	150 MHz	D-Type	190 çA	Non-Inverted	1	4.9 ns	2.7 V	3.6 V	20-SO	Surface Mount	20-SOIC			Positive Edge			0.209 "	5.3 mm

Catalog

Enhanced Product 3.3-V Abt Octal D-Type Flip-Flops With Clear

Key Features

• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification PedigreeSupports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)Typical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CSupports Unregulated Battery Operation Down to 2.7 VBuffered Clock and Direct-Clear InputsIndividual Data Input to Each Flip-FlopIoffSupports Partial Power-Down-Mode OperationBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 500 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification PedigreeSupports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)Typical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CSupports Unregulated Battery Operation Down to 2.7 VBuffered Clock and Direct-Clear InputsIndividual Data Input to Each Flip-FlopIoffSupports Partial Power-Down-Mode OperationBus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown ResistorsLatch-Up Performance Exceeds 500 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Description

These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. These octal D-type flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The ’LVTH273 devices are positive-edge-triggered flip-flops with a direct-clear input. Information at the data (D) inputs meeting the setup-time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.