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16-TSSOP
Integrated Circuits (ICs)

SN74LV595APWRG3

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Texas Instruments

EIGHT-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

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16-TSSOP
Integrated Circuits (ICs)

SN74LV595APWRG3

Active
Texas Instruments

EIGHT-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LV595APWRG3
FunctionSerial to Parallel, Serial
Logic TypeShift Register
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package16-TSSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.86
10$ 0.77
25$ 0.73
100$ 0.60
250$ 0.56
500$ 0.50
1000$ 0.39
Digi-Reel® 1$ 0.86
10$ 0.77
25$ 0.73
100$ 0.60
250$ 0.56
500$ 0.50
1000$ 0.39
Tape & Reel (TR) 2000$ 0.37
6000$ 0.35
10000$ 0.33
Texas InstrumentsLARGE T&R 1$ 0.83
100$ 0.56
250$ 0.43
1000$ 0.29

Description

General part information

SN74LV595A-Q1 Series

The SN74LV595A-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.

The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV595A-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.