Specification	SN74LVC2G132DCTR

Current - Output High, Low [x]	32 mA
Current - Output High, Low [y]	32 mA
Current - Quiescent (Max) [Max]	10 µA
Features	Schmitt Trigger
Input Logic Level - High [Max]	3.33 V
Input Logic Level - High [Min]	1.16 V
Input Logic Level - Low [Max]	1.87 V
Input Logic Level - Low [Min]	0.39 V
Logic Type	NAND Gate
Max Propagation Delay @ V, Max CL	5 ns
Mounting Type	Surface Mount
Number of Circuits	2
Number of Inputs	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-40 °C
Supplier Device Package	SM8
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	1.65 V

SN74LVC2G132 Series

2-ch, 2-input, 1.65-V to 5.5-V NAND gates with Schmitt-Trigger inputs

Part	Operating Temperature [Max]	Operating Temperature [Min]	Number of Circuits	Package / Case [y]	Package / Case	Package / Case [y]	Current - Output High, Low [y]	Current - Output High, Low [x]	Logic Type	Number of Inputs	Features	Mounting Type	Input Logic Level - Low [Min]	Input Logic Level - Low [Max]	Current - Quiescent (Max) [Max]	Voltage - Supply [Max]	Voltage - Supply [Min]	Max Propagation Delay @ V, Max CL	Input Logic Level - High [Min]	Input Logic Level - High [Max]	Supplier Device Package	Supplier Device Package [y]	Supplier Device Package [x]
Texas Instruments SN74LVC2G132DCUT	125 °C	-40 °C	2	2.3 mm	8-VFSOP	0.091 in	32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V
Texas Instruments SN74LVC2G132DCTR	125 °C	-40 °C	2				32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V	SM8
Texas Instruments SN74LVC2G132DCUR	125 °C	-40 °C	2	2.3 mm	8-VFSOP	0.091 in	32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V
Texas Instruments SN74LVC2G132YEPR	85 °C	-40 °C	2		8-XFBGA DSBGA		32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V	8-DSBGA (1.9x0.9)	0.9	1.9
Texas Instruments 74LVC2G132DCTRG4	125 °C	-40 °C	2				32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	6 ns	1.16 V	3.33 V	SM8
Texas Instruments 74LVC2G132DCUTG4	125 °C	-40 °C	2	2.3 mm	8-VFSOP	0.091 in	32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	6 ns	1.16 V	3.33 V
Texas Instruments 74LVC2G132DCURG4	125 °C	-40 °C	2	2.3 mm	8-VFSOP	0.091 in	32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	6 ns	1.16 V	3.33 V
Texas Instruments SN74LVC2G132YZPR	85 °C	-40 °C	2		8-XFBGA DSBGA		32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V	8-DSBGA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.58
		10	$ 0.51
		25	$ 0.48
		100	$ 0.39
		250	$ 0.36
		500	$ 0.31
		1000	$ 0.25
	Digi-Reel®	1	$ 0.58
		10	$ 0.51
		25	$ 0.48
		100	$ 0.39
		250	$ 0.36
		500	$ 0.31
		1000	$ 0.25
	Tape & Reel (TR)	3000	$ 0.22
		6000	$ 0.21
		15000	$ 0.20
		30000	$ 0.19
Texas Instruments	LARGE T&R	1	$ 0.42
		100	$ 0.29
		250	$ 0.22
		1000	$ 0.15

Description

General part information

SN74LVC2G132 Series

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCCoperation.

The SN74LVC2G132 contains two inverters and performs the Boolean function Y =A ⋅ Bor Y =A+Bin positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Documents

Technical documentation and resources

SN74LVC2G132DCTR

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SN74LVC2G132DCTR

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Technical Specifications

SN74LVC2G132 Series

Pricing

Description

SN74LVC2G132 Series

Documents

Live Insertion

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

How to Select Little Logic (Rev. A)

Logic Guide (Rev. AB)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Understanding Advanced Bus-Interface Products Design Guide

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Selecting the Right Level Translation Solution (Rev. A)

LOGIC Pocket Data Book (Rev. B)

Design Summary for WCSP Little Logic (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Little Logic Guide 2018 (Rev. G)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

Low-Voltage Logic (LVC) Designer's Guide

Standard Linear & Logic for PCs, Servers & Motherboards

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Dual 2-Input NAND Gate With Schmitt-Trigger Inputs datasheet (Rev. D)

CMOS Power Consumption and CPD Calculation (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

LVC Characterization Information

Texas Instruments Little Logic Application Report

Signal Switch Data Book (Rev. A)

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices