
PL133-67OI-R
UnknownPL133 SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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PL133-67OI-R
UnknownPL133 SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
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Technical Specifications
Parameters and characteristics for this part
| Specification | PL133-67OI-R |
|---|---|
| Differential - Input:Output | False |
| Frequency - Max [Max] | 150 MHz |
| Input | LVCMOS |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVCMOS |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Ratio - Input:Output [custom] | 1:6 |
| Supplier Device Package | 16-TSSOP |
| Type | Fanout Buffer (Distribution) |
| Voltage - Supply [Max] | 3.63 V |
| Voltage - Supply [Min] | 2.25 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Microchip Direct | T/R | 1 | $ 3.82 | |
| 25 | $ 3.16 | |||
| 100 | $ 2.88 | |||
| 1000 | $ 2.78 | |||
| 5000 | $ 2.76 | |||
Description
General part information
PL133-47 Series
The PL133-97 is an advanced fanout buffer design for high performance, low-power, small form factor applications. The PL133-97 accepts a reference clock input from DC to 150 MHz and provides 9 outputs of the same frequency.The PL133-97 is offered in a QFN-16L 3mm x 3mm package and it offers the best phase noise, additive jitter performance, and lowest power consumption of any comparable IC. The PL133-97 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled.
Documents
Technical documentation and resources