Deep-Dive with AI
Search across all available documentation for this part.
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LVC138AZQNR |
|---|---|
| Circuit | 1 x 3:8 |
| Current - Output High, Low | 24 mA |
| Independent Circuits | 1 |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 20-VFBGA |
| Supplier Device Package | 20-BGA MICROSTAR JUNIOR (4x3) |
| Type | Decoder/Demultiplexer |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
| Voltage Supply Source | Single Supply |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74LVC138A-Q1 Series
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation.
The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
Documents
Technical documentation and resources
