Texas Instruments

The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.

The DS99R124AQ converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. The DS99R124AQ converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided. Adjustable input equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces the medium-induced deterministic jitter. EMI is minimized by the use of low voltage differential signaling, output state select feature, and additional output spread spectrum generation. With fewer wires to the physical interface of the display, FPD-Link output with LVDS technology is ideal for high speed, low power and low EMI data transfer. The DS99R124AQ is offered in a 48-pin WQFN package and is specified over the automotive AEC-Q100 Grade 2 temperature range of -40˚C to +105˚C. The DS99R124AQ converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. The DS99R124AQ converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided. Adjustable input equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces the medium-induced deterministic jitter. EMI is minimized by the use of low voltage differential signaling, output state select feature, and additional output spread spectrum generation. With fewer wires to the physical interface of the display, FPD-Link output with LVDS technology is ideal for high speed, low power and low EMI data transfer. The DS99R124AQ is offered in a 48-pin WQFN package and is specified over the automotive AEC-Q100 Grade 2 temperature range of -40˚C to +105˚C.

The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and LVDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins. The DS99R421 incorporates a single serialized LVDS signal on the high-speed I/O. Embedded clock LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the converter output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding is used to support AC-Coupled interconnects. The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and LVDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins. The DS99R421 incorporates a single serialized LVDS signal on the high-speed I/O. Embedded clock LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the converter output edge rate for the operating frequency range EMI is further reduced. In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding is used to support AC-Coupled interconnects.

The DSD1608 is a CMOS, monolithic, 8-channel digital-to-analog converter which supports both PCM audio data format and direct stream digital (DSD) audio data format. The device includes an 8× digital interpolation filter and a digital DSD filter with three selectable frequency-response curves, followed by Texas Instruments’ enhanced multilevel delta-sigma modulator, which employs 4th-order noise shaping and 8-level amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. Sampling rates up to 192 kHz for the PCM mode and 64 × 44.1 kHz for the DSD mode are supported. A full set of user-programmable functions is accessible through a 4-wire serial control port, which supports register write and read functions. The DSD1608 supports the time-division-multiplexed command and audio data (TDMCA) format. The DSD1608 is available in a 52-pin TQFP package. The DSD1608 is a CMOS, monolithic, 8-channel digital-to-analog converter which supports both PCM audio data format and direct stream digital (DSD) audio data format. The device includes an 8× digital interpolation filter and a digital DSD filter with three selectable frequency-response curves, followed by Texas Instruments’ enhanced multilevel delta-sigma modulator, which employs 4th-order noise shaping and 8-level amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter. Sampling rates up to 192 kHz for the PCM mode and 64 × 44.1 kHz for the DSD mode are supported. A full set of user-programmable functions is accessible through a 4-wire serial control port, which supports register write and read functions. The DSD1608 supports the time-division-multiplexed command and audio data (TDMCA) format. The DSD1608 is available in a 52-pin TQFP package.

The DSD1792A is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1792A provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1792A accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1792A also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through a 4-wire serial control port, which supports register write and readback functions. The DSD1792A also supports the time-division-multiplexed command and audio (TDMCA) data format. The DSD1792A is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1792A provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1792A accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1792A also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through a 4-wire serial control port, which supports register write and readback functions. The DSD1792A also supports the time-division-multiplexed command and audio (TDMCA) data format.

The DSD1793 is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1793 provides balanced voltage outputs, allowing the user to optimize analog performance externally. The DSD1793 accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1793 also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an I2C-compatible serial port. The DSD1793 is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1793 provides balanced voltage outputs, allowing the user to optimize analog performance externally. The DSD1793 accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1793 also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an I2C-compatible serial port.

The DSD1794A is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1794A provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1794A accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1794A also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an I2C-compatible serial port. The DSD1794A is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1794A provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1794A accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1794A also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an I2C-compatible serial port.

The DSD1796 is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1796 provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1796 accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1796 also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an SPI serial control port, which supports register write and readback functions. The DSD1796 also supports the time-division-multiplexed command and audio (TDMCA) data format. The DSD1796 is a monolithic CMOS integrated circuit that includes stereo digital-to-analog converters and support circuitry in a small 28-lead SSOP package. The data converters use TI’s advanced-segment DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter. The DSD1796 provides balanced current outputs, allowing the user to optimize analog performance externally. The DSD1796 accepts the PCM and DSD audio data formats, providing easy interfacing to audio DSP and decoder chips. The DSD1796 also interfaces with external digital filter devices (DF1704, DF1706, PMD200). Sampling rates up to 200 kHz are supported. A full set of user-programmable functions is accessible through an SPI serial control port, which supports register write and readback functions. The DSD1796 also supports the time-division-multiplexed command and audio (TDMCA) data format.