DS92LX162110-MHz to 50-MHz DC-balanced Channel Link III serializer with bi-directional control channel | Integrated Circuits (ICs) | 3 | Active | The DS92LX1621 / DS92LX1622 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex back channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bi-directional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The sleep function provides a power-savings mode and a remote wake up interrupt for signaling of a remote device.
The Serializer is offered in a 32-pin WQFN package, and Deserializer is offered in a 40-pin WQFN package.
The DS92LX1621 / DS92LX1622 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex back channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bi-directional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The sleep function provides a power-savings mode and a remote wake up interrupt for signaling of a remote device.
The Serializer is offered in a 32-pin WQFN package, and Deserializer is offered in a 40-pin WQFN package. |
DS92LX162210-MHz to 50-MHz DC-balanced Channel Link III deserializer with bi-directional control channel | Interface | 3 | Active | The DS92LX1621 / DS92LX1622 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex back channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bi-directional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The sleep function provides a power-savings mode and a remote wake up interrupt for signaling of a remote device.
The Serializer is offered in a 32-pin WQFN package, and Deserializer is offered in a 40-pin WQFN package.
The DS92LX1621 / DS92LX1622 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex back channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bi-directional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) or parity bit to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The sleep function provides a power-savings mode and a remote wake up interrupt for signaling of a remote device.
The Serializer is offered in a 32-pin WQFN package, and Deserializer is offered in a 40-pin WQFN package. |
DS92LX212110-MHz to 50-MHz DC-balanced Channel Link III Bi-Directional control serializer | Integrated Circuits (ICs) | 2 | Active | The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.
In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.
The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.
In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages. |
DS92LX212210 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Deserializer | Serializers, Deserializers | 3 | Active | The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.
In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.
The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.
In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages. |
| Drivers, Receivers, Transceivers | 2 | Obsolete | |
| Drivers, Receivers, Transceivers | 2 | Obsolete | |
| Drivers, Receivers, Transceivers | 3 | Obsolete | |
| Interface | 5 | Obsolete | |
| Drivers, Receivers, Transceivers | 2 | Active | The DS96F172 and the DS96F174 are high speed quad differential line drivers designed to meet EIA-485 Standards. The DS96F172 and the DS96F174 offer improved performance due to the use of L-FAST bipolar technology. The use of LFAST technology allows the DS96F172 and DS96F174 to operate at higher speeds while minimizing power consumption.
The DS96F172 and the DS96F174 have TRI-STATE outputs and are optimized for balanced multipoint data bus transmission at rates up to 15 Mbps. The drivers have wide positive and negative common mode range for multipoint applications in noisy environments. Positive and negative current-limiting is provided which protects the drivers from line fault conditions over a +12V to −7.0V common mode range. A thermal shutdown feature is also provided. The DS96F172 features an active high and active low Enable, common to all four drivers. The DS96F174 features separate active high Enables for each driver pair.
The DS96F172 and the DS96F174 are high speed quad differential line drivers designed to meet EIA-485 Standards. The DS96F172 and the DS96F174 offer improved performance due to the use of L-FAST bipolar technology. The use of LFAST technology allows the DS96F172 and DS96F174 to operate at higher speeds while minimizing power consumption.
The DS96F172 and the DS96F174 have TRI-STATE outputs and are optimized for balanced multipoint data bus transmission at rates up to 15 Mbps. The drivers have wide positive and negative common mode range for multipoint applications in noisy environments. Positive and negative current-limiting is provided which protects the drivers from line fault conditions over a +12V to −7.0V common mode range. A thermal shutdown feature is also provided. The DS96F172 features an active high and active low Enable, common to all four drivers. The DS96F174 features separate active high Enables for each driver pair. |
| Integrated Circuits (ICs) | 1 | Active | The DS96F173 and the DS96F175 are high speed quad differential line receivers designed to meet the EIA-485 standard. The DS96F173 and the DS96F175 offer improved performance due to the use of L-FAST bipolar technology. The use of LFAST technology allows the DS96F173 and DS96F175 to operate at higher speeds while minimizing power consumption.
The DS96F173 and the DS96F175 have TRI-STATE outputs and are optimized for balanced multipoint data bus transmission at rates up to 15 Mbps. The receivers feature high input impedance, input hysteresis for increased noise immunity, and input sensitivity of 200 mV over a common mode input voltage range of −7V to +12V. The receivers are therefore suitable for multipoint applications in noisy environments. The DS96F173 features an active high and active low Enable, common to all four receivers. The DS96F175 features separate active high Enables for each receiver pair.
The DS96F173 and the DS96F175 are high speed quad differential line receivers designed to meet the EIA-485 standard. The DS96F173 and the DS96F175 offer improved performance due to the use of L-FAST bipolar technology. The use of LFAST technology allows the DS96F173 and DS96F175 to operate at higher speeds while minimizing power consumption.
The DS96F173 and the DS96F175 have TRI-STATE outputs and are optimized for balanced multipoint data bus transmission at rates up to 15 Mbps. The receivers feature high input impedance, input hysteresis for increased noise immunity, and input sensitivity of 200 mV over a common mode input voltage range of −7V to +12V. The receivers are therefore suitable for multipoint applications in noisy environments. The DS96F173 features an active high and active low Enable, common to all four receivers. The DS96F175 features separate active high Enables for each receiver pair. |
