Catalog
3-MHz to 40-MHz DC-balanced 24-bit LVDS deserializer
Key Features
• 3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data TransmissionsCapable to Drive Shielded Twisted-Pair CableUser Selectable Clock Edge for Parallel Data on Both Transmitter and ReceiverInternal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding RequiredIndividual Power-Down Controls for Both Transmitter and ReceiverEmbedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock NeededAll Codes RDL (Random Data Lock) to Support Live-Pluggable ApplicationsLOCK Output Flag to Ensure Data Integrity at Receiver SideBalanced TSETUP/THOLDbetween RCLK and RDATA on Receiver SidePTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO EffectsAll LVCMOS Inputs and Control Pins have Internal PulldownOn-Chip Filters for PLLs on Transmitter and ReceiverIntegrated 100Ω Input Termination on Receiver4 mA Receiver Output Drive48-Pin TQFP and 48-Pin WQFN PackagesPure CMOS .35 μm ProcessPower Supply Range 3.3V ± 10%Temperature Range 0°C to +70°C8 kV HBM ESD ToleranceAll trademarks are the property of their respective owners.3 MHz–40 MHz Clock Embedded and DC-Balancing 24:1 and 1:24 Data TransmissionsCapable to Drive Shielded Twisted-Pair CableUser Selectable Clock Edge for Parallel Data on Both Transmitter and ReceiverInternal DC Balancing Encode/Decode – Supports AC-Coupling Interface with no External Coding RequiredIndividual Power-Down Controls for Both Transmitter and ReceiverEmbedded Clock CDR (Clock and Data Recovery) on Receiver and no External Source of Reference Clock NeededAll Codes RDL (Random Data Lock) to Support Live-Pluggable ApplicationsLOCK Output Flag to Ensure Data Integrity at Receiver SideBalanced TSETUP/THOLDbetween RCLK and RDATA on Receiver SidePTO (Progressive Turn-On) LVCMOS Outputs to Reduce EMI and Minimize SSO EffectsAll LVCMOS Inputs and Control Pins have Internal PulldownOn-Chip Filters for PLLs on Transmitter and ReceiverIntegrated 100Ω Input Termination on Receiver4 mA Receiver Output Drive48-Pin TQFP and 48-Pin WQFN PackagesPure CMOS .35 μm ProcessPower Supply Range 3.3V ± 10%Temperature Range 0°C to +70°C8 kV HBM ESD ToleranceAll trademarks are the property of their respective owners.
Description
AI
The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS99R105/DS99R106 incorporates LVDS signaling on the high-speed I/O. LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
