DS92LX2122 Series
10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Deserializer
Manufacturer: Texas Instruments
Catalog
10 - 50 MHz DC-Balanced Channel Link III Bi-Directional Control Deserializer
Key Features
• GeneralUp to 1050 Mbits/sec Data Throughput10 MHz to 50 MHz Input Clock SupportSupports 18-bit Color Depth(RGB666 + HS, VS, DE)Embedded Clock with DC Balanced Coding toSupport AC-Coupled InterconnectsCapable to Drive up to 10 Meters ShieldedTwisted-PairBi-Directional Control Interface Channelwith I2C SupportI2C Interface for DeviceConfiguration. Single-Pin ID AddressingUp to 4 GPI on DES and GPO on SERAT-SPEED BIST Diagnosis Feature to ValidateLink IntegrityIndividual Power-Down Controls for both SERand DESUser-Selectable Clock Edge for Parallel Dataon both SER and DESIntegrated Termination Resistors1.8V- or 3.3V-Compatible Parallel Bus InterfaceSingle Power Supply at 1.8VIEC 61000–4–2 ESD CompliantTemperature Range −40°C to +85°CDESERIALIZER — DS92LX2122No Reference Clock Required on DeserializerProgrammable Receive EqualizationLOCK Output Reporting Pin to EnsureEMI/EMC MitigationProgrammable Spread Spectrum (SSCG) OutputsReceiver Output Drive Strength Control (RDS)Receiver Staggered OutputsGeneralUp to 1050 Mbits/sec Data Throughput10 MHz to 50 MHz Input Clock SupportSupports 18-bit Color Depth(RGB666 + HS, VS, DE)Embedded Clock with DC Balanced Coding toSupport AC-Coupled InterconnectsCapable to Drive up to 10 Meters ShieldedTwisted-PairBi-Directional Control Interface Channelwith I2C SupportI2C Interface for DeviceConfiguration. Single-Pin ID AddressingUp to 4 GPI on DES and GPO on SERAT-SPEED BIST Diagnosis Feature to ValidateLink IntegrityIndividual Power-Down Controls for both SERand DESUser-Selectable Clock Edge for Parallel Dataon both SER and DESIntegrated Termination Resistors1.8V- or 3.3V-Compatible Parallel Bus InterfaceSingle Power Supply at 1.8VIEC 61000–4–2 ESD CompliantTemperature Range −40°C to +85°CDESERIALIZER — DS92LX2122No Reference Clock Required on DeserializerProgrammable Receive EqualizationLOCK Output Reporting Pin to EnsureEMI/EMC MitigationProgrammable Spread Spectrum (SSCG) OutputsReceiver Output Drive Strength Control (RDS)Receiver Staggered Outputs
Description
AI
The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.
In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.
The DS92LX2121/DS92LX2122 chipset offers a Channel Link III interface with a high-speed forward channel and a full-duplex control channel for data transmission over a single differential pair. The DS92LX2121/DS92LX2122 incorporates differential signaling on both the high-speed and bi-directional back channel control data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with a bi-directional back channel control bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bi-directional back channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bi-directional back channel control information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce cable width, connector size and pins.
In addition, the Deserializer provides input equalization to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
A sleep function provides a power-savings mode when the high speed forward channel and embedded bi-directional control channel are not needed.
The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.
