| Drivers, Receivers, Transceivers | 3 | Active | The DS90C031 is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C031 accepts TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE function that may be used to disable the output stage, thus dropping the device to a low idle power state of 11 mW typical.
In addition, the DS90C031 provides power-off high impedance LVDS outputs. This feature assures minimal loading effect on the LVDS bus lines when VCCis not present. The DS90C031 and companion line receiver (DS90C032) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications.
The DS90C031 is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C031 accepts TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE function that may be used to disable the output stage, thus dropping the device to a low idle power state of 11 mW typical.
In addition, the DS90C031 provides power-off high impedance LVDS outputs. This feature assures minimal loading effect on the LVDS bus lines when VCCis not present. The DS90C031 and companion line receiver (DS90C032) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. |
DS90C032BLVDS quad CMOS differential line receiver | Integrated Circuits (ICs) | 6 | Active | The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device supports data rates in excess of 155.5 Mbps (77.7 MHz) and uses Low Voltage Differential Signaling (LVDS) technology.
The DS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032B provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCCis not present.
The DS90C032B and companion line driver (DS90C031B) provide a new alternative to high power pseudo-ECL devices for high-speed point-to-point interface applications.
The DS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device supports data rates in excess of 155.5 Mbps (77.7 MHz) and uses Low Voltage Differential Signaling (LVDS) technology.
The DS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032B provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCCis not present.
The DS90C032B and companion line driver (DS90C031B) provide a new alternative to high power pseudo-ECL devices for high-speed point-to-point interface applications. |
| Interface | 1 | Active | The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications.
The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. |
| Integrated Circuits (ICs) | 1 | Active | The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications.
The DS90C032 is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
The DS90C032 accepts low voltage differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions.
The DS90C032 provides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present.
The DS90C032 and companion line driver (DS90C031) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. |
DS90C124-Q15-MHz to 35-MHz DC-balanced 24-bit automotive FPD-Link II deserializer | Interface | 2 | Active | The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.
The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects.
The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.
The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects. |
DS90C185Low Power FPD-Link (LVDS) Serializer | Integrated Circuits (ICs) | 1 | Active | The DS90C185 is a low-power serializer for portable battery-powered applications that reduces the size of the RGB interface between the host GPU and the display.
24-bit RGB plus three video control signals are serialized and translated to LVDS-compatible levels and sent as a 4 data + clock (4D+C) reduced-width LVDS compatible interface. The LVDS Interface is compatible with FPD-Link (1) deserializers and many LVDS based displays. These interfaces are commonly supported in LCD modules with "LVDS" or FPD-Link / FlatLink single-pixel input interfaces.
Displays up to 1400x1050 at 60 fps are supported with 24-bpp color depth. 18 bpp may also be supported by a dedicated mode with a 3D+C output. Power dissipation is minimized by the full LVCMOS design and 1.8-V powered core and VDDIOrails.
The DS90C185 is offered in the small 48-pin WQFN package and features single 1.8-V supply operation for minimum power dissipation (50 mW typ).
The DS90C185 is a low-power serializer for portable battery-powered applications that reduces the size of the RGB interface between the host GPU and the display.
24-bit RGB plus three video control signals are serialized and translated to LVDS-compatible levels and sent as a 4 data + clock (4D+C) reduced-width LVDS compatible interface. The LVDS Interface is compatible with FPD-Link (1) deserializers and many LVDS based displays. These interfaces are commonly supported in LCD modules with "LVDS" or FPD-Link / FlatLink single-pixel input interfaces.
Displays up to 1400x1050 at 60 fps are supported with 24-bpp color depth. 18 bpp may also be supported by a dedicated mode with a 3D+C output. Power dissipation is minimized by the full LVCMOS design and 1.8-V powered core and VDDIOrails.
The DS90C185 is offered in the small 48-pin WQFN package and features single 1.8-V supply operation for minimum power dissipation (50 mW typ). |
DS90C187Low Power Dual Pixel FPD-Link (LVDS) Serializer | Integrated Circuits (ICs) | 1 | Active | The DS90C187 is a low power Serializer for portable battery powered that reduces the size of the RGB interface between the host GPU and the Display.
The DS90C187 Serializer is designed to support dual pixel data transmission between a Host and a Flat Panel Display at resolutions of up to QXGA (2048x1536) at 60 Hz. The transmitter converts up to 48 bits (Dual Pixel 24-bit color) of 1.8-V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width interface LVDS compatible data streams.
DS90C187 supports 3 modes of operation.
In dual pixel in / dual pixel out mode, the device can drive up to QXGA 2048x1536 at 60Hz or up to QSXGA 2560x2048 at 30Hz. In this mode, the device converts 2 channels of 24 bit RGB data into 2 channels of 4D+C LVDS streams. For all the modes, the device supports 18bpp and 24bpp color.
The DS90C187 is offered in a small 92 pin dual row VQFN package and features single 1.8 V supply for minimal power dissipation.
The DS90C187 is a low power Serializer for portable battery powered that reduces the size of the RGB interface between the host GPU and the Display.
The DS90C187 Serializer is designed to support dual pixel data transmission between a Host and a Flat Panel Display at resolutions of up to QXGA (2048x1536) at 60 Hz. The transmitter converts up to 48 bits (Dual Pixel 24-bit color) of 1.8-V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width interface LVDS compatible data streams.
DS90C187 supports 3 modes of operation.
In dual pixel in / dual pixel out mode, the device can drive up to QXGA 2048x1536 at 60Hz or up to QSXGA 2560x2048 at 30Hz. In this mode, the device converts 2 channels of 24 bit RGB data into 2 channels of 4D+C LVDS streams. For all the modes, the device supports 18bpp and 24bpp color.
The DS90C187 is offered in a small 92 pin dual row VQFN package and features single 1.8 V supply for minimal power dissipation. |
DS90C189-Q1Low Power 1.8-V Dual Pixel FPD-Link (LVDS) Serializer | Interface | 2 | Active | The DS90C189-Q1 is a low power bridge for automotive applications that reduces the size of the RGB interface between the host GPU and the Display.
The DS90C189-Q1Bridge is designed to support single pixel data transmission between a Host and a Flat Panel Display at resolutions of up to QXGA (2048x1536) at 60 Hz. The transmitter converts up to 24 bits (Single Pixel 24-bit color) of 1.8-V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width interface LVDS compatible data streams.
DS90C189-Q1 supports 2 modes of operation.
For all the modes, the device supports 24bpp color.
The DS90C189-Q1 is offered in a small 64 pin QFN package and features single 1.8 V supply for minimal power dissipation.
The DS90C189-Q1 is a low power bridge for automotive applications that reduces the size of the RGB interface between the host GPU and the Display.
The DS90C189-Q1Bridge is designed to support single pixel data transmission between a Host and a Flat Panel Display at resolutions of up to QXGA (2048x1536) at 60 Hz. The transmitter converts up to 24 bits (Single Pixel 24-bit color) of 1.8-V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width interface LVDS compatible data streams.
DS90C189-Q1 supports 2 modes of operation.
For all the modes, the device supports 24bpp color.
The DS90C189-Q1 is offered in a small 64 pin QFN package and features single 1.8 V supply for minimal power dissipation. |
DS90C241-Q15-MHz to 35-MHz DC-balanced 24-bit automotive FPD-Link II serializer | Interface | 3 | Active | The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.
The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects.
The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins.
The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects. |
| Integrated Circuits (ICs) | 1 | Obsolete | |
