| Integrated Circuits (ICs) | 4 | Active | 4-Bit Magnitude Comparator |
CD74HCT864-ch, 2-input, 4.5-V to 5.5-V XOR (exclusive OR) gates with TTL-compatible CMOS inputs | Integrated Circuits (ICs) | 5 | Active | This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic.
This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic. |
CD74HCU04-Q1Automotive 6-ch, 4.5-V to 5.5-V inverters with TTL-compatible CMOS inputs | Integrated Circuits (ICs) | 21 | Active | The CD74HCU04 unbuffered hex inverter utilizes silicon-gate CMOS technology to achieve operation speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. These devices are especially useful in crystal oscillator and analog applications.
The CD74HCU04 unbuffered hex inverter utilizes silicon-gate CMOS technology to achieve operation speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. These devices are especially useful in crystal oscillator and analog applications. |
CDC1113.3-V LVPECL differential clock driver | Integrated Circuits (ICs) | 3 | Active | The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50-transmission lines.
When the output-enable (OE\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).
The VREFoutput can be strapped to the CLKIN\ input for a single-ended CLKIN input.
The CDC111 is characterized for operation from 0°C to 70°C.
The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50-transmission lines.
When the output-enable (OE\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).
The VREFoutput can be strapped to the CLKIN\ input for a single-ended CLKIN input.
The CDC111 is characterized for operation from 0°C to 70°C. |
CDC2033.3-V 6-bit inverter/clock driver | Gates and Inverters | 4 | Active | The CDC203 contains six independent inverters. The device performs the Boolean function Y = A\. It is designed specifically for applications requiring low skew between switching outputs.
The CDC203 is characterized for operation from 25°C to 70°C.
The CDC203 contains six independent inverters. The device performs the Boolean function Y = A\. It is designed specifically for applications requiring low skew between switching outputs.
The CDC203 is characterized for operation from 25°C to 70°C. |
CDC2045-V 6-bit inverter / clock driver | Integrated Circuits (ICs) | 1 | Active | The CDC204 contains six independent inverters. The device performs the Boolean function Y = A\. It is designed specifically for applications requiring low skew between switching outputs.
The CDC204 is characterized for operation from TA= 25°C to 70°C.
The CDC204 contains six independent inverters. The device performs the Boolean function Y = A\. It is designed specifically for applications requiring low skew between switching outputs.
The CDC204 is characterized for operation from TA= 25°C to 70°C. |
| Unclassified | 6 | Active | |
CDC2351-Q1Enhanced Product 1-line to 10-line clock driver with 3-state outputs | Integrated Circuits (ICs) | 10 | Active | The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE\) input disables the outputs to a high-impedance state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351 operates at nominal 3.3-V VCC.
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.
The CDC2351 is characterized for operation from 0°C to 70°C. The CDC2351Q is characterized for operation over the full automotive temperature range of -40°C to 125°C.
The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE\) input disables the outputs to a high-impedance state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351 operates at nominal 3.3-V VCC.
The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.
The CDC2351 is characterized for operation from 0°C to 70°C. The CDC2351Q is characterized for operation over the full automotive temperature range of -40°C to 125°C. |
CDC2509C1-to-9 PLL clock driver for SDRAM applications | Clock/Timing | 3 | NRND | The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2509C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground.
The CDC2509C is characterized for operation from 0°C to 85°C.
For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039).
The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2509C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground.
The CDC2509C is characterized for operation from 0°C to 85°C.
For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039). |
CDC2510C3.3-V PLL clock driver with support for PC SDRAM registered DIMM design support document rev. 1.2 | Clock/Timing | 5 | NRND | The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC= 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground.
The CDC2510C is characterized for operation from 0°C to 85°C.
For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039).
The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC= 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground.
The CDC2510C is characterized for operation from 0°C to 85°C.
For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039). |
