Texas Instruments

The CDC391 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control (T\/C) inputs, various combinations of true and complementary outputs can be obtained. The output-enable () input is provided to disable the outputs to a high-impedance state. The CDC391 is characterized for operation from -40°C to 85°C. The CDC391 contains a clock-driver circuit that distributes one input signal to six outputs with minimum skew for clock distribution. Through the use of the polarity-control (T\/C) inputs, various combinations of true and complementary outputs can be obtained. The output-enable () input is provided to disable the outputs to a high-impedance state. The CDC391 is characterized for operation from -40°C to 85°C.

The CDC3RL02 is a two-channel clock fan-out buffer and is designed for use in portable end-equipment, such as mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities. The device buffers a single clock source, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each input can enable a single clock output. The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3V signal (peak-to-peak). CDC3RL02 is designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3V to 5.5V and outputs 1.8V, 50mA. This 1.8V supply is externally available to provide regulated power to peripheral devices such as a TCXO. The CDC3RL02 is offered in a 0.4mm pitch die size ball grid array (DSBGA) package (0.8mm × 1.6mm), also known as wafer-level chip-scale (WCSP) package, and is optimized for very low standby current consumption. The CDC3RL02 is a two-channel clock fan-out buffer and is designed for use in portable end-equipment, such as mobile phones, that require clock buffering with minimal additive phase noise and fan-out capabilities. The device buffers a single clock source, such as a temperature compensated crystal oscillator (TCXO) to multiple peripherals. The device has two clock request inputs (CLK_REQ1 and CLK_REQ2), each input can enable a single clock output. The CDC3RL02 accepts square or sine waves at the master clock input (MCLK_IN), eliminating the need for an AC coupling capacitor. The smallest acceptable sine wave is a 0.3V signal (peak-to-peak). CDC3RL02 is designed to offer minimal channel-to-channel skew, additive output jitter, and additive phase noise. The adaptive clock output buffers offer controlled slew-rate over a wide capacitive loading range which minimizes EMI emissions, maintains signal integrity, and minimizes ringing caused by signal reflections on the clock distribution lines. The CDC3RL02 has an integrated Low-Drop-Out (LDO) voltage regulator which accepts input voltages from 2.3V to 5.5V and outputs 1.8V, 50mA. This 1.8V supply is externally available to provide regulated power to peripheral devices such as a TCXO. The CDC3RL02 is offered in a 0.4mm pitch die size ball grid array (DSBGA) package (0.8mm × 1.6mm), also known as wafer-level chip-scale (WCSP) package, and is optimized for very low standby current consumption.