CDC2510C Series

3.3-V PLL clock driver with support for PC SDRAM registered DIMM design support document rev. 1.2

Catalog

3.3-V PLL clock driver with support for PC SDRAM registered DIMM design support document rev. 1.2

Part	Mounting Type	Number of Circuits	Supplier Device Package	Ratio - Input:Output [custom]	Package / Case	Package / Case	Type	Input	Operating Temperature [Max]	Frequency - Max [Max]	Output	Voltage - Supply [Max]	Voltage - Supply [Min]	PLL
Texas Instruments CDC2510CPWG4	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	85 °C	125 MHz	Clock	3.6 V	3 V	Yes with Bypass
Texas Instruments CDC2510CPW	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	85 °C	125 MHz	Clock	3.6 V	3 V	Yes with Bypass
Texas Instruments CDC2510PWR	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	70 °C	125 MHz	Clock	3.6 V	3 V	Yes with Bypass
Texas Instruments CDC2510APWR	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	70 °C		Clock	3.6 V	3 V	Yes with Bypass
Texas Instruments CDC2510BPWR	Surface Mount	1	24-TSSOP	1:10	24-TSSOP	0.173 in 4.4 mm	PLL Clock Driver	Clock	70 °C	125 MHz	Clock	3.6 V	3 V	Yes with Bypass

Catalog

3.3-V PLL clock driver with support for PC SDRAM registered DIMM design support document rev. 1.2

Key Features

• UseCDCVF2510Aas a Replacement for this DeviceDesigned to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2Spread Spectrum Clock CompatibleOperating Frequency 25 MHz to 125 MHzStatic tPhase Error Distribution at 66 MHz to 100 MHz is ±150 psDrop-In Replacement for TI CDC2510A With Enhanced PerformanceJitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|Available in Plastic 24-Pin TSSOPPhase-Lock Loop Clock Distribution for Synchronous DRAM ApplicationsDistributes One Clock Input to One Bank of Ten OutputsExternal Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock InputOn-Chip Series Damping ResistorsNo External RC Network RequiredOperates at 3.3 VUseCDCVF2510Aas a Replacement for this DeviceDesigned to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2Spread Spectrum Clock CompatibleOperating Frequency 25 MHz to 125 MHzStatic tPhase Error Distribution at 66 MHz to 100 MHz is ±150 psDrop-In Replacement for TI CDC2510A With Enhanced PerformanceJitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|Available in Plastic 24-Pin TSSOPPhase-Lock Loop Clock Distribution for Synchronous DRAM ApplicationsDistributes One Clock Input to One Bank of Ten OutputsExternal Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock InputOn-Chip Series Damping ResistorsNo External RC Network RequiredOperates at 3.3 V

Description

The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC= 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground. The CDC2510C is characterized for operation from 0°C to 85°C. For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039). The CDC2510C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2510C operates at VCC= 3.3 V . It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2510C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground. The CDC2510C is characterized for operation from 0°C to 85°C. For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039).