CD74ACT112 Series

Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset

Catalog

Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset

Part	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Function	Type	Current - Output High, Low	Package / Case	Package / Case [x]	Package / Case [y]	Trigger Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Mounting Type	Number of Elements	Clock Frequency	Number of Bits per Element	Input Capacitance	Supplier Device Package	Max Propagation Delay @ V, Max CL	Current - Quiescent (Iq)
Texas Instruments CD74ACT112M	Complementary	125 °C	-55 °C	Reset Set(Preset)	JK Type	24 mA	16-SOIC	0.154 in	3.9 mm	Negative Edge	4.5 V	5.5 V	Surface Mount	2	100 MHz	1	10 pF	16-SOIC	10.3 ns	4 çA

Catalog

Dual Negative-Edge Triggered J-K Flip-Flops with Set and Reset

Key Features

• Inputs Are TTL-Voltage CompatibleSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015Inputs Are TTL-Voltage CompatibleSpeed of Bipolar F, AS, and S, With Significantly Reduced Power ConsumptionBalanced Propagation Delays±24-mA Output Drive CurrentFanout to 15 F DevicesSCR-Latchup-Resistant CMOS Process and Circuit DesignExceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

Description

The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.