| Analog Switches, Multiplexers, Demultiplexers | 1 | Active | CD40x7B CMOS analog multiplexers or demultiplexers are digitally controlled analog switches having low ON impedance, low OFF leakage current, and internal address decoding. When these devices are used as demultiplexers, the channel in or out terminals are the outputs and the common out or in terminals are the inputs. In addition, the ON resistance is relatively constant over the full input-signal range.
The CD4067B is a 16-channel multiplexer with four binary control inputs, A, B, C, D, and an inhibit input, arranged so that any combination of the inputs selects one switch.
A logic "1" present at the inhibit input turns all channels off.
The CD40x7B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (P and PWR suffixes).
CD40x7B CMOS analog multiplexers or demultiplexers are digitally controlled analog switches having low ON impedance, low OFF leakage current, and internal address decoding. When these devices are used as demultiplexers, the channel in or out terminals are the outputs and the common out or in terminals are the inputs. In addition, the ON resistance is relatively constant over the full input-signal range.
The CD4067B is a 16-channel multiplexer with four binary control inputs, A, B, C, D, and an inhibit input, arranged so that any combination of the inputs selects one switch.
A logic "1" present at the inhibit input turns all channels off.
The CD40x7B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (P and PWR suffixes). |
CD4098BCMOS Dual Monostable Multivibrator | Multivibrators | 6 | Active | CD4098B dual monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application.
An external resistor (RX) and an external capacitor (CX) control the timing for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. The time delay from trigger input to output transition (trigger progagation delay) and the time delay from set input to output transition (reset progagation delay) are independent of RXand CX.
Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) input are provided for triggering from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused (-TR) input should be tied to VDD. A RESET (on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. However, if an entire section of the CD4098B is not used, its RESET should be tied to VSS. See Table 1.
In normal operation the circuit triggers (extends the output pulse one period) on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q\ is connected to -TR when leading-edge triggering (+TR) is used or Q is connected to +TR when trailing-edge triggering (-TR) is used.
The time period (T) for this multivibrator can be approximated by: TX= ½ RXCXfor CX0.01 uF. Time periods as a function of RXfor values of CXand VDDare given in Fig. 8. Values of T vary from unit to unit and as a function of voltage, temperature, and RXCX.
The minimum value of external resistance, RX, is 5 k. The maximum value of external capacitance, CX, is 100uF. Fig.9 shows time periods as a function of CXfor values of RXand VDD.
The output pulse width has variations of ±2.5% typically, over the temperature range of -55°C to 125°C for CX= 1000 pF and RX= 100 k.
For power supply variations of ±5%, the output pulse width has variations of ±0.5% typically, for VDD= 10 V and 15 V and ±1% typically, for VDD= 5 V at CX= 1000 pF and RX= 5 k.
These types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
The CD4098B is similar to type MC14528.
CD4098B dual monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application.
An external resistor (RX) and an external capacitor (CX) control the timing for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. The time delay from trigger input to output transition (trigger progagation delay) and the time delay from set input to output transition (reset progagation delay) are independent of RXand CX.
Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) input are provided for triggering from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused (-TR) input should be tied to VDD. A RESET (on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. However, if an entire section of the CD4098B is not used, its RESET should be tied to VSS. See Table 1.
In normal operation the circuit triggers (extends the output pulse one period) on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q\ is connected to -TR when leading-edge triggering (+TR) is used or Q is connected to +TR when trailing-edge triggering (-TR) is used.
The time period (T) for this multivibrator can be approximated by: TX= ½ RXCXfor CX0.01 uF. Time periods as a function of RXfor values of CXand VDDare given in Fig. 8. Values of T vary from unit to unit and as a function of voltage, temperature, and RXCX.
The minimum value of external resistance, RX, is 5 k. The maximum value of external capacitance, CX, is 100uF. Fig.9 shows time periods as a function of CXfor values of RXand VDD.
The output pulse width has variations of ±2.5% typically, over the temperature range of -55°C to 125°C for CX= 1000 pF and RX= 100 k.
For power supply variations of ±5%, the output pulse width has variations of ±0.5% typically, for VDD= 10 V and 15 V and ±1% typically, for VDD= 5 V at CX= 1000 pF and RX= 5 k.
These types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
The CD4098B is similar to type MC14528. |
| Multivibrators | 3 | Active | CD4098B dual monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application.
An external resistor (RX) and an external capacitor (CX) control the timing for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. The time delay from trigger input to output transition (trigger progagation delay) and the time delay from set input to output transition (reset progagation delay) are independent of RXand CX.
Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) input are provided for triggering from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused (-TR) input should be tied to VDD. A RESET (on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. However, if an entire section of the CD4098B is not used, its RESET should be tied to VSS. See Table 1.
In normal operation the circuit triggers (extends the output pulse one period) on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q\ is connected to -TR when leading-edge triggering (+TR) is used or Q is connected to +TR when trailing-edge triggering (-TR) is used.
The time period (T) for this multivibrator can be approximated by: TX= ½ RXCXfor CX0.01 uF. Time periods as a function of RXfor values of CXand VDDare given in Fig. 8. Values of T vary from unit to unit and as a function of voltage, temperature, and RXCX.
The minimum value of external resistance, RX, is 5 k. The maximum value of external capacitance, CX, is 100uF. Fig.9 shows time periods as a function of CXfor values of RXand VDD.
The output pulse width has variations of ±2.5% typically, over the temperature range of -55°C to 125°C for CX= 1000 pF and RX= 100 k.
For power supply variations of ±5%, the output pulse width has variations of ±0.5% typically, for VDD= 10 V and 15 V and ±1% typically, for VDD= 5 V at CX= 1000 pF and RX= 5 k.
These types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
The CD4098B is similar to type MC14528.
CD4098B dual monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application.
An external resistor (RX) and an external capacitor (CX) control the timing for the circuit. Adjustment of RXand CXprovides a wide range of output pulse widths from the Q and Q\ terminals. The time delay from trigger input to output transition (trigger progagation delay) and the time delay from set input to output transition (reset progagation delay) are independent of RXand CX.
Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) input are provided for triggering from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused (-TR) input should be tied to VDD. A RESET (on low level) is provided for immediate termination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. However, if an entire section of the CD4098B is not used, its RESET should be tied to VSS. See Table 1.
In normal operation the circuit triggers (extends the output pulse one period) on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q\ is connected to -TR when leading-edge triggering (+TR) is used or Q is connected to +TR when trailing-edge triggering (-TR) is used.
The time period (T) for this multivibrator can be approximated by: TX= ½ RXCXfor CX0.01 uF. Time periods as a function of RXfor values of CXand VDDare given in Fig. 8. Values of T vary from unit to unit and as a function of voltage, temperature, and RXCX.
The minimum value of external resistance, RX, is 5 k. The maximum value of external capacitance, CX, is 100uF. Fig.9 shows time periods as a function of CXfor values of RXand VDD.
The output pulse width has variations of ±2.5% typically, over the temperature range of -55°C to 125°C for CX= 1000 pF and RX= 100 k.
For power supply variations of ±5%, the output pulse width has variations of ±0.5% typically, for VDD= 10 V and 15 V and ±1% typically, for VDD= 5 V at CX= 1000 pF and RX= 5 k.
These types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
The CD4098B is similar to type MC14528. |
CD4099BCMOS 8-Bit Addressable Latch | Integrated Circuits (ICs) | 7 | Active | CD4099B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.
The CD4099B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline package (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4099B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.
The CD4099B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline package (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). |
| Latches | 1 | Active | CD4099B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.
The CD4099B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline package (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4099B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit is addressed (by means of input A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs.
A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE RESET is at a low level, the latch acts as a 1-of-8 demultiplexer; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level.
The CD4099B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic package (E suffix), 16-lead small-outline package (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). |
| Integrated Circuits (ICs) | 4 | Active | CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOLstandard.
The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOLstandard.
The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). |
| Logic | 10 | Active | CD4502B is a hex noninverting buffer with 3-state outputs having high sink- and source-current capability. Two disable controls are provided, one of which controls four buffers and the other controls the remaining two buffers.
The CD4503B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4502B is a hex noninverting buffer with 3-state outputs having high sink- and source-current capability. Two disable controls are provided, one of which controls four buffers and the other controls the remaining two buffers.
The CD4503B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). |
CD4504B-EPCMOS Hex Voltage-Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation | Logic | 9 | Active | CD4504B hex voltage level-shifter consists of six circuits which shift input signals from the VCClogic level to the VDDlogic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCCHIGH logic state. When the SELECT input is a LOW logic state, each circuit translates signals from one CMOS level to another.
The CD4504B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4504B hex voltage level-shifter consists of six circuits which shift input signals from the VCClogic level to the VDDlogic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCCHIGH logic state. When the SELECT input is a LOW logic state, each circuit translates signals from one CMOS level to another.
The CD4504B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and MT suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). |
| Integrated Circuits (ICs) | 8 | Active | CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the reset line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input.
The CD4508B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).
The CD4508B is similar to industry type MC14508.
CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the reset line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input.
The CD4508B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).
The CD4508B is similar to industry type MC14508. |
| Logic | 2 | Active | CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the reset line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input.
The CD4508B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).
The CD4508B is similar to industry type MC14508.
CD4508B dual 4-bit latch contains two identical 4-bit latches with separate STROBE, RESET, and OUTPUT DISABLE control. With the STROBE line in the high state, the data on the "D" inputs appear at the corresponding "Q" outputs provided the DISABLE line is in the low state. Changing the STROBE line to the low state locks the data into the latch. A high on the reset line forces the outputs to a low level regardless of the state of the STROBE input. The outputs are forced to the high-impedance state for bus line applications by a high level on the DISABLE input.
The CD4508B types are supplied in 24-lead hermetic dual-in-line ceramic packages (F3A suffix), 24-lead dual-in-line plastic packages (E suffix), 24-lead small-outline packages (M, M96, and NSR suffixes), and 24-lead thin shrink small-outline packages (PW and PWR suffixes).
The CD4508B is similar to industry type MC14508. |
