CD4502B Series

6-ch, 3-V to 18-V inverters

Catalog

6-ch, 3-V to 18-V inverters

Part	Number of Elements	Logic Type	Package / Case	Package / Case [x]	Package / Case [y]	Number of Bits per Element	Output Type	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Package / Case
Texas Instruments CD4502BM	1	Buffer Inverting	16-SOIC	0.154 in	3.9 mm	6	Push-Pull	16-SOIC	125 °C	-55 °C	Surface Mount	3.4 mA	20.4 mA	18 V	3 V
Texas Instruments CD4502BNSR	1	Buffer Inverting	16-SOIC			6	Push-Pull	16-SO	125 °C	-55 °C	Surface Mount	3.4 mA	20.4 mA	18 V	3 V	0.209 "	5.3 mm
Texas Instruments CD4502BPW	1	Buffer Inverting	16-TSSOP	0.173 in	4.4 mm	6	Push-Pull	16-TSSOP	125 °C	-55 °C	Surface Mount	3.4 mA	20.4 mA	18 V	3 V
Texas Instruments CD4502BM96	1	Buffer Inverting	16-SOIC	0.154 in	3.9 mm	6	Push-Pull	16-SOIC	125 °C	-55 °C	Surface Mount	3.4 mA	20.4 mA	18 V	3 V

Catalog

6-ch, 3-V to 18-V inverters

Key Features

• 2 TTL-load output drive capability3-state outputsCommon output-disable controlInhibit control100% tested for quiescent current at 20 V5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"Noise Margin (full package-temperature range) =1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VApplications:3-state hex inverter for interfacing IC's with data busesCOS/MOS to TTL hex buffer2 TTL-load output drive capability3-state outputsCommon output-disable controlInhibit control100% tested for quiescent current at 20 V5-V, 10-V, and 15-V parametric ratingsMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"Noise Margin (full package-temperature range) =1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 VApplications:3-state hex inverter for interfacing IC's with data busesCOS/MOS to TTL hex buffer

Description

CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOLstandard. The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes). CD4502B consists of six inverter/buffers with 3-state outputs. A logic "1" on the OUTPUT DISABLE input produces a high-impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic "1" on the INHIBIT input switches all six outputs to logic "0" if the OUTPUT DISABLE input is a logic "0". This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC "B"-series IOLstandard. The CD4502B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).