| Video Processing | 1 | NRND | |
TPS651929-Channel Level Shifter for LCD Displays with GPM | Integrated Circuits (ICs) | 1 | Active | The TPS65192 is a 9 channel level-shifter intended for use in LCD display applications such as TVs and monitors. The device converts the logic-level signals generated by the Timing Controller (T-CON) to the high-level signals used by the display panel.
The 9 level shifter channels are organized as two groups. Channels 1 through 7 are powered from VGH1and VGL, and channels 8 and 9 are powered from VGH2and VGL. Each level-shifter channel features low impedance output stages that achieve fast rise and fall times even when driving the capacitive loading typically present in LCD display applications.
Level shifter channels 1 through 6 support gate voltage shaping, which can be used to improve picture quality by reducing image sticking. Novel decoding logic enables a single flicker clock signal to control gate voltage shaping for all CLK channels without the need for synchronization. The device also supports the use of multiple flicker clocks. The rate of decay is set by an external resistor or resistor network connected to the RE pin.
A tenth level shifter channel specially configured with a comparator input stage allows designers to implement panel discharging during power-down.
The TPS65192 is a 9 channel level-shifter intended for use in LCD display applications such as TVs and monitors. The device converts the logic-level signals generated by the Timing Controller (T-CON) to the high-level signals used by the display panel.
The 9 level shifter channels are organized as two groups. Channels 1 through 7 are powered from VGH1and VGL, and channels 8 and 9 are powered from VGH2and VGL. Each level-shifter channel features low impedance output stages that achieve fast rise and fall times even when driving the capacitive loading typically present in LCD display applications.
Level shifter channels 1 through 6 support gate voltage shaping, which can be used to improve picture quality by reducing image sticking. Novel decoding logic enables a single flicker clock signal to control gate voltage shaping for all CLK channels without the need for synchronization. The device also supports the use of multiple flicker clocks. The rate of decay is set by an external resistor or resistor network connected to the RE pin.
A tenth level shifter channel specially configured with a comparator input stage allows designers to implement panel discharging during power-down. |
| Amplifiers | 1 | Active | |
| Translators, Level Shifters | 1 | LTB | |
TPS6519615-Channel Level Shifter for Large Size TVs | Integrated Circuits (ICs) | 1 | LTB | The TPS65196 provides a highly integrated level shifter solution intended for TV and monitor applications using GIP technology. The device features a built-in state machine that generates 14 output signals from the five input signals provided by the timing controller (T-CON). In addition, the TPS65196 generates a signal to discharge the display panel during power-down.
To ensure proper start-up of the LCD panel, the TPS65196 includes a programmable soft-start feature that ramps the CLK output current from zero to its maximum value during the initial frames after power-up.
Level shifter outputs are forced to a safe state (VGL) during abnormal panel operation, which is indicated by the T-CON using the EO and GST signals. The IC is also placed in the same safe state if it gets too hot. Normal behavior restarts automatically (synchronized to the start of the next frame) when the device temperature is cool enough for safe operation.
The TPS65196 provides a highly integrated level shifter solution intended for TV and monitor applications using GIP technology. The device features a built-in state machine that generates 14 output signals from the five input signals provided by the timing controller (T-CON). In addition, the TPS65196 generates a signal to discharge the display panel during power-down.
To ensure proper start-up of the LCD panel, the TPS65196 includes a programmable soft-start feature that ramps the CLK output current from zero to its maximum value during the initial frames after power-up.
Level shifter outputs are forced to a safe state (VGL) during abnormal panel operation, which is indicated by the T-CON using the EO and GST signals. The IC is also placed in the same safe state if it gets too hot. Normal behavior restarts automatically (synchronized to the start of the next frame) when the device temperature is cool enough for safe operation. |
TPS651978-Channel Level-Shifter supporting 2-, 3-Channel Charge-Sharing and Panel Discharge | Integrated Circuits (ICs) | 3 | Active | The TPS65197/B is an 8-channel level-shifter with discharge function intended for use in LCD display applications such as Notebooks, Monitors and TVs.
The device converts the timing-controller (T-CON) logic-level signals to the high-level signals needed by the gate-in-panel (GIP) display.
The clock outputs, CLKOUTx, support normal level shifting operation and 2-channel or 3-channel charge-sharing, which can be used to improve picture quality and power consumption. At power down, all outputs follow their input signals as long as possible; when the discharge function is used, the outputs are pulled high (VGH).
The TPS65197 implements a logic reset to ignore wrong T-CON signals after the rising STV edge which forces all 6 output clocks to VGL1. The next CLKIN1 rising edge unlocks the logic and enables normal operation. The TPS65197B does not have the logic reset and always follows its input signals.
The TPS65197/B is an 8-channel level-shifter with discharge function intended for use in LCD display applications such as Notebooks, Monitors and TVs.
The device converts the timing-controller (T-CON) logic-level signals to the high-level signals needed by the gate-in-panel (GIP) display.
The clock outputs, CLKOUTx, support normal level shifting operation and 2-channel or 3-channel charge-sharing, which can be used to improve picture quality and power consumption. At power down, all outputs follow their input signals as long as possible; when the discharge function is used, the outputs are pulled high (VGH).
The TPS65197 implements a logic reset to ignore wrong T-CON signals after the rising STV edge which forces all 6 output clocks to VGL1. The next CLKIN1 rising edge unlocks the logic and enables normal operation. The TPS65197B does not have the logic reset and always follows its input signals. |
| Video Processing | 2 | Active | |
| Evaluation and Demonstration Boards and Kits | 10 | Obsolete | |
TPS65200Li+ Battery Charger With WLED Driver and Current Shunt Monitor | Integrated Circuits (ICs) | 2 | Active | The TPS65200 device integrates a high-efficiency, USB-friendly switched-mode charger with OTG support for single-cell Li-ion and Li-polymer batteries, D+D– detection, a 50-mA fixed-voltage LDO, a high-efficiency WLED boost converter, and high-accuracy current-shunt monitor into a single chip.
The TPS65200 comes in a tiny, 2.8-mm × 2.6-mm, 36-pin, 0.4-mm pitch die size ball grid array (DSBGA).
The TPS65200 device integrates a high-efficiency, USB-friendly switched-mode charger with OTG support for single-cell Li-ion and Li-polymer batteries, D+D– detection, a 50-mA fixed-voltage LDO, a high-efficiency WLED boost converter, and high-accuracy current-shunt monitor into a single chip.
The TPS65200 comes in a tiny, 2.8-mm × 2.6-mm, 36-pin, 0.4-mm pitch die size ball grid array (DSBGA). |
TPS65216Integrated power management (PMIC) for ARM® Cortex™-A8/A9 SOCs and FPGAs | Power Management - Specialized | 2 | Active | The TPS65216 is a single chip, power-management IC (PMIC) specifically designed to support the AMIC110, AMIC120, AM335x, and AM437x line of processors in line-powered (5 V) applications. The device is characterized across a –40°C to +105°C temperature range, making it suitable for various industrial applications.
The TPS65216 is specifically designed to provide power management for all the functionalities of the AMIC110, AMIC120, AM335x, and AM437x. The DC/DC converters DCDC1 through DCDC4 are intended to power the core, MPU, DDR memory, and 3.3-V analog and I/O, respectively. LDO1 provides the 1.8-V analog and I/O for the processor. GPIO2 allows for warm reset of the DCDC1 and DCDC2 converters. The I2C interface allows the user to enable and disable all voltage regulators, the load switch, and GPIOs. Additionally, UVLO and supervisor voltage thresholds, power-up sequence, and power-down sequence can be programmed through I2C. Interrupts for overtemperature, overcurrent, and undervoltage can be monitored as well. The supervisor monitors DCDC1 through DCDC4 and LDO1. The supervisor has two settings, one for typical undervoltage tolerance (STRICT = 0b), and one for tight undervoltage and overvoltage tolerances (STRICT = 1b). A power-good signal indicates proper regulation of the five voltage regulators.
Three hysteretic step-down converters are targeted at providing power for the processor core, MPU, and DDRx memory. The default output voltages for each converter can be adjusted through the I2C interface. DCDC1 and DCDC2 feature dynamic voltage scaling to provide power at all operating points of the processor. DCDC1 and DCDC2 also have programmable slew rates to help protect processor components. DCDC3 remains powered while the processor is in sleep mode to maintain power to DDRx memory.
The TPS65216 device is available in a 48-pin VQFN package (6 mm × 6 mm, 0.4-mm pitch).
The TPS65216 is a single chip, power-management IC (PMIC) specifically designed to support the AMIC110, AMIC120, AM335x, and AM437x line of processors in line-powered (5 V) applications. The device is characterized across a –40°C to +105°C temperature range, making it suitable for various industrial applications.
The TPS65216 is specifically designed to provide power management for all the functionalities of the AMIC110, AMIC120, AM335x, and AM437x. The DC/DC converters DCDC1 through DCDC4 are intended to power the core, MPU, DDR memory, and 3.3-V analog and I/O, respectively. LDO1 provides the 1.8-V analog and I/O for the processor. GPIO2 allows for warm reset of the DCDC1 and DCDC2 converters. The I2C interface allows the user to enable and disable all voltage regulators, the load switch, and GPIOs. Additionally, UVLO and supervisor voltage thresholds, power-up sequence, and power-down sequence can be programmed through I2C. Interrupts for overtemperature, overcurrent, and undervoltage can be monitored as well. The supervisor monitors DCDC1 through DCDC4 and LDO1. The supervisor has two settings, one for typical undervoltage tolerance (STRICT = 0b), and one for tight undervoltage and overvoltage tolerances (STRICT = 1b). A power-good signal indicates proper regulation of the five voltage regulators.
Three hysteretic step-down converters are targeted at providing power for the processor core, MPU, and DDRx memory. The default output voltages for each converter can be adjusted through the I2C interface. DCDC1 and DCDC2 feature dynamic voltage scaling to provide power at all operating points of the processor. DCDC1 and DCDC2 also have programmable slew rates to help protect processor components. DCDC3 remains powered while the processor is in sleep mode to maintain power to DDRx memory.
The TPS65216 device is available in a 48-pin VQFN package (6 mm × 6 mm, 0.4-mm pitch). |
