| Analog Front End (AFE) | 2 | Active | |
AFE7225Dual-Channel, 12-Bit, 125-MSPS ADC & Dual-Channel 12-Bit 250-MSPS DAC With Auxiliary ADC and DACs | Integrated Circuits (ICs) | 2 | Active | The AFE7225/7222 is an analog front end designed for full- or half-duplex radios. Over-sampling transmit 12-bit DACs provide output frequencies from baseband to Nyquist. Under-sampling receive 12-bit ADCs allow analog inputs from baseband to ~230MHz. Most blocks within the AFE7225/7222 are independently controlled for optimization of power consumption versus utilization. Two auxiliary control 12-bit DACs and a dual input auxiliary monitoring 12-bit ADC are available via serial interface. Digital features include QMC (quadrature modulation correction), interpolation, decimation, RMS/peak power meter and mixers with independent NCOs for RX and TX path.
The AFE7225/7222 is available in a 64-pin 9x9mm QFN package (RGC). The AFE7225/7222 is built on Texas Instrument’s low power analog CMOS process and is specified over the full industrial temperature range (–40°C to 85°C).
The AFE7225/7222 is an analog front end designed for full- or half-duplex radios. Over-sampling transmit 12-bit DACs provide output frequencies from baseband to Nyquist. Under-sampling receive 12-bit ADCs allow analog inputs from baseband to ~230MHz. Most blocks within the AFE7225/7222 are independently controlled for optimization of power consumption versus utilization. Two auxiliary control 12-bit DACs and a dual input auxiliary monitoring 12-bit ADC are available via serial interface. Digital features include QMC (quadrature modulation correction), interpolation, decimation, RMS/peak power meter and mixers with independent NCOs for RX and TX path.
The AFE7225/7222 is available in a 64-pin 9x9mm QFN package (RGC). The AFE7225/7222 is built on Texas Instrument’s low power analog CMOS process and is specified over the full industrial temperature range (–40°C to 85°C). |
AFE74222-transmit, 2-receive RF-sampling transceiver, 10-MHz to 6-GHz, max 1200-MHz IBW | Analog Front End (AFE) | 2 | Active | The AFE7422 is a dual-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enables direct RF sampling into the C-band frequency range without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multimission systems.
The DAC signal paths support interpolation and digital up conversion options that deliver up to 1200 MHz of signal bandwidth. The differential output path includes a digital step attenuator (DSA), which enables tuning of output power.
Each ADC input path includes a dual DSA and RF and Digital power detectors. Flexible decimation options provide optimization of data bandwidth and a decimation bypass mode is also available for widest signal bandwidth.
An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15 Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output.
The AFE7422 is a dual-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enables direct RF sampling into the C-band frequency range without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multimission systems.
The DAC signal paths support interpolation and digital up conversion options that deliver up to 1200 MHz of signal bandwidth. The differential output path includes a digital step attenuator (DSA), which enables tuning of output power.
Each ADC input path includes a dual DSA and RF and Digital power detectors. Flexible decimation options provide optimization of data bandwidth and a decimation bypass mode is also available for widest signal bandwidth.
An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15 Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output. |
AFE74444-transmit, 4-receive RF-sampling transceiver, 10-MHz to 6-GHz, max 600-MHz IBW | Analog Front End (AFE) | 2 | Active | The AFE7444 is a quad-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enables direct RF sampling into the C-band frequency range without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multimission systems.
The DAC signal paths support interpolation and digital up conversion options that deliver up to 800 MHz of signal bandwidth. The differential output path includes a digital step attenuator (DSA), which enables tuning of output power.
Each ADC input path includes a dual DSA and RF and Digital power detectors. Flexible decimation options provide optimization of data bandwidth.
An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15 Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output.
The AFE7444 is a quad-channel, wideband, RF-sampling analog front end (AFE) based on 14-bit, 9-GSPS DACs and 14-bit, 3-GSPS ADCs. With operation at an RF of up to 6 GHz, this device enables direct RF sampling into the C-band frequency range without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multimission systems.
The DAC signal paths support interpolation and digital up conversion options that deliver up to 800 MHz of signal bandwidth. The differential output path includes a digital step attenuator (DSA), which enables tuning of output power.
Each ADC input path includes a dual DSA and RF and Digital power detectors. Flexible decimation options provide optimization of data bandwidth.
An 8-lane (8 TX + 8 RX) subclass-1 compliant JESD204B interface operates at up to 15 Gbps. A bypassable on-chip PLL simplifies clock operation with an optional clock output. |
AFE76814-transmit, 2-receive RF-sampling transceiver, 100-MHz to 5.2-GHz, max 1200-MHz IBW | Analog Front End (AFE) | 1 | Active | The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital Pre-Distortion) of the Power Amplifier (PA) on the transmitter path.
The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector and various digital power detectors to assist AGC control for receiver channels, and two RF overload detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as 4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by allowing use of a lower frequency reference clock.
The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital Pre-Distortion) of the Power Amplifier (PA) on the transmitter path.
The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector and various digital power detectors to assist AGC control for receiver channels, and two RF overload detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as 4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by allowing use of a lower frequency reference clock. |
AFE76854-transmit, 4-receive RF-sampling transceiver, 100-MHz to 5.2-GHz, max 1200-MHz IBW, single DUC/D | Integrated Circuits (ICs) | 1 | Active | The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital Pre-Distortion) of the Power Amplifier (PA) on the transmitter path.
The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector and various digital power detectors to assist AGC control for receiver channels, and two RF overload detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as 4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by allowing use of a lower frequency reference clock.
The AFE76xx is a family of high performance, quad/dual channel, 14-bit, integrated RF sampling analog front ends (AFEs) with 9 GSPS DACs and 3 GSPS ADCs, capable of synthesizing and digitizing wideband signals. High dynamic range allows the AFE76xx to generate and digitize 3G/4G signals for wireless base stations. In TDD mode, the receiver channel can be configured to dynamically switching between traffic receiver (TDD RX) status and wideband feedback receiver (TDD FB) status to assist DPD (Digital Pre-Distortion) of the Power Amplifier (PA) on the transmitter path.
The AFE76xx family has integrated DSA on the receiver channels and also supports DSA equivalent functionality on the transmitter channels. Each receiver channel has one analog RF peak power detector and various digital power detectors to assist AGC control for receiver channels, and two RF overload detectors for device reliability protection. The AFE76xx family has 8 of JESD204B compatible SerDes transceivers running up to 15 Gbps. The devices have up to two DUCs per TX channel and two DDCs per RX channel, with multiple interpolation/decimation rates and digital quadrature modulators/demodulators with independent, frequency flexible NCOs. The devices support more than 1000 MHz (800 MHz as 4T4R) RF signal bandwidth in single-band mode, and up to 800 MHz (300 MHz as 4T4R) RF signal bandwidth per band in dual-band mode. A low jitter PLL/VCO simplifies the sampling clock generation by allowing use of a lower frequency reference clock. |
| RF Transceiver ICs | 2 | Active | |
AFE7728DDual-channel RF transceiver with dual feedback paths and integrated CFR/DPD - 200MHz | RF and Wireless | 1 | Active | The AFE77xxD is a pin-compatible family of high-performance, multichannel transceivers, integrating four (AFE7768D/AFE7769D) or two (AFE7728D) direct up-conversion transmitter chains, four (AFE7768D/AFE7769D) or two (AFE7728D) direct down-conversion receiver chains, two wideband RF sampling digitizing auxiliary chains (feedback paths) and low-power Digital Pre-Distortion (DPD) engine for Power Amplifier (PA) linearization. The high dynamic range of the transmitter and receiver chains enables wireless base stations to transmit and receive 2G, 3G, 4G, and 5G signals. The integrated Crest Factor Reduction (CFR) unit helps reduce the Peak-to-Average Ratio (PAR) of the input signal for more efficient transmission through the Power Amplifier. The integrated hardware accelerated DPD estimator and corrector provides flexible and efficient DPD solution for PA linearization. The integrated DPD engine corrects the distortion due to PA nonlinearity for signals up to 200MHz (AFE77x8D) / 300MHz (AFE7769D) instantaneous bandwidth, and within up to 650MHz (AFE77x8D) / 730MHz (AFE7769D) DPD expanded bandwidth. A dedicated GaN corrector addresses the long-term nonlinear memory effects due to charge trapping of GaN PAs.
The low power dissipation and high density channel integration of the AFE77xxD allow the device to address the power and size constraints of 4G and 5G base stations. The wideband and high dynamic range feedback path can assist the DPD of the power amplifiers in the transmitter chain through smart data capture at various intercepting points. The available 29.5Gbps SerDes speed can help reduce the number of lanes required to transfer the data in and out of the device.
Each receiver chain of the AFE77xxD includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated antialiasing low pass filters with programmable bandwidth, driving continuous-time sigma-delta ADCs. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz (AFE77x8D) / 300 MHz (AFE7769D). Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.
Each transmitter chain includes two 14-bit, 3.3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.
Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3.3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. The FB path integrates two independent NCOs, which allow for a fast switching between two observed RF input bands.
The synthesizer section integrates four fractional-N RF PLLs that can generate four different RF LOs, allowing the device to support up to two different bands, each one configured as two transmitters, two receivers, and one feedback path (with AFE7768D/AFE7769D), or one transmitter, one receiver, and one feedback path (with AFE7728D) .
The AFE77xxD is a pin-compatible family of high-performance, multichannel transceivers, integrating four (AFE7768D/AFE7769D) or two (AFE7728D) direct up-conversion transmitter chains, four (AFE7768D/AFE7769D) or two (AFE7728D) direct down-conversion receiver chains, two wideband RF sampling digitizing auxiliary chains (feedback paths) and low-power Digital Pre-Distortion (DPD) engine for Power Amplifier (PA) linearization. The high dynamic range of the transmitter and receiver chains enables wireless base stations to transmit and receive 2G, 3G, 4G, and 5G signals. The integrated Crest Factor Reduction (CFR) unit helps reduce the Peak-to-Average Ratio (PAR) of the input signal for more efficient transmission through the Power Amplifier. The integrated hardware accelerated DPD estimator and corrector provides flexible and efficient DPD solution for PA linearization. The integrated DPD engine corrects the distortion due to PA nonlinearity for signals up to 200MHz (AFE77x8D) / 300MHz (AFE7769D) instantaneous bandwidth, and within up to 650MHz (AFE77x8D) / 730MHz (AFE7769D) DPD expanded bandwidth. A dedicated GaN corrector addresses the long-term nonlinear memory effects due to charge trapping of GaN PAs.
The low power dissipation and high density channel integration of the AFE77xxD allow the device to address the power and size constraints of 4G and 5G base stations. The wideband and high dynamic range feedback path can assist the DPD of the power amplifiers in the transmitter chain through smart data capture at various intercepting points. The available 29.5Gbps SerDes speed can help reduce the number of lanes required to transfer the data in and out of the device.
Each receiver chain of the AFE77xxD includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated antialiasing low pass filters with programmable bandwidth, driving continuous-time sigma-delta ADCs. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz (AFE77x8D) / 300 MHz (AFE7769D). Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.
Each transmitter chain includes two 14-bit, 3.3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.
Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3.3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. The FB path integrates two independent NCOs, which allow for a fast switching between two observed RF input bands.
The synthesizer section integrates four fractional-N RF PLLs that can generate four different RF LOs, allowing the device to support up to two different bands, each one configured as two transmitters, two receivers, and one feedback path (with AFE7768D/AFE7769D), or one transmitter, one receiver, and one feedback path (with AFE7728D) . |
AFE7768DFour-channel RF transceiver with dual feedback paths and integrated CFR/DPD - 200MHz | RF and Wireless | 1 | Active | The AFE77xxD is a pin-compatible family of high-performance, multichannel transceivers, integrating four (AFE7768D/AFE7769D) or two (AFE7728D) direct up-conversion transmitter chains, four (AFE7768D/AFE7769D) or two (AFE7728D) direct down-conversion receiver chains, two wideband RF sampling digitizing auxiliary chains (feedback paths) and low-power Digital Pre-Distortion (DPD) engine for Power Amplifier (PA) linearization. The high dynamic range of the transmitter and receiver chains enables wireless base stations to transmit and receive 2G, 3G, 4G, and 5G signals. The integrated Crest Factor Reduction (CFR) unit helps reduce the Peak-to-Average Ratio (PAR) of the input signal for more efficient transmission through the Power Amplifier. The integrated hardware accelerated DPD estimator and corrector provides flexible and efficient DPD solution for PA linearization. The integrated DPD engine corrects the distortion due to PA nonlinearity for signals up to 200MHz (AFE77x8D) / 300MHz (AFE7769D) instantaneous bandwidth, and within up to 650MHz (AFE77x8D) / 730MHz (AFE7769D) DPD expanded bandwidth. A dedicated GaN corrector addresses the long-term nonlinear memory effects due to charge trapping of GaN PAs.
The low power dissipation and high density channel integration of the AFE77xxD allow the device to address the power and size constraints of 4G and 5G base stations. The wideband and high dynamic range feedback path can assist the DPD of the power amplifiers in the transmitter chain through smart data capture at various intercepting points. The available 29.5Gbps SerDes speed can help reduce the number of lanes required to transfer the data in and out of the device.
Each receiver chain of the AFE77xxD includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated antialiasing low pass filters with programmable bandwidth, driving continuous-time sigma-delta ADCs. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz (AFE77x8D) / 300 MHz (AFE7769D). Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.
Each transmitter chain includes two 14-bit, 3.3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.
Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3.3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. The FB path integrates two independent NCOs, which allow for a fast switching between two observed RF input bands.
The synthesizer section integrates four fractional-N RF PLLs that can generate four different RF LOs, allowing the device to support up to two different bands, each one configured as two transmitters, two receivers, and one feedback path (with AFE7768D/AFE7769D), or one transmitter, one receiver, and one feedback path (with AFE7728D) .
The AFE77xxD is a pin-compatible family of high-performance, multichannel transceivers, integrating four (AFE7768D/AFE7769D) or two (AFE7728D) direct up-conversion transmitter chains, four (AFE7768D/AFE7769D) or two (AFE7728D) direct down-conversion receiver chains, two wideband RF sampling digitizing auxiliary chains (feedback paths) and low-power Digital Pre-Distortion (DPD) engine for Power Amplifier (PA) linearization. The high dynamic range of the transmitter and receiver chains enables wireless base stations to transmit and receive 2G, 3G, 4G, and 5G signals. The integrated Crest Factor Reduction (CFR) unit helps reduce the Peak-to-Average Ratio (PAR) of the input signal for more efficient transmission through the Power Amplifier. The integrated hardware accelerated DPD estimator and corrector provides flexible and efficient DPD solution for PA linearization. The integrated DPD engine corrects the distortion due to PA nonlinearity for signals up to 200MHz (AFE77x8D) / 300MHz (AFE7769D) instantaneous bandwidth, and within up to 650MHz (AFE77x8D) / 730MHz (AFE7769D) DPD expanded bandwidth. A dedicated GaN corrector addresses the long-term nonlinear memory effects due to charge trapping of GaN PAs.
The low power dissipation and high density channel integration of the AFE77xxD allow the device to address the power and size constraints of 4G and 5G base stations. The wideband and high dynamic range feedback path can assist the DPD of the power amplifiers in the transmitter chain through smart data capture at various intercepting points. The available 29.5Gbps SerDes speed can help reduce the number of lanes required to transfer the data in and out of the device.
Each receiver chain of the AFE77xxD includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated antialiasing low pass filters with programmable bandwidth, driving continuous-time sigma-delta ADCs. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz (AFE77x8D) / 300 MHz (AFE7769D). Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the RX chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.
Each transmitter chain includes two 14-bit, 3.3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.
Each FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3.3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. The FB path integrates two independent NCOs, which allow for a fast switching between two observed RF input bands.
The synthesizer section integrates four fractional-N RF PLLs that can generate four different RF LOs, allowing the device to support up to two different bands, each one configured as two transmitters, two receivers, and one feedback path (with AFE7768D/AFE7769D), or one transmitter, one receiver, and one feedback path (with AFE7728D) . |
| RF Transceiver ICs | 3 | Active | |
