ADS8902B20-bit, 500-kSPS, one-channel SAR ADC with internal VREF buffer, internal LDO and enhanced SPI | Integrated Circuits (ICs) | 2 | Active | The ADS8900B, ADS8902B, and ADS8904B (ADS890xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 20-bit successive-approximation-register (SAR) analog-to-digital converters (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS891xB (18-bit) and ADS892xB (16-bit) resolution variants.
The ADS89xxB boosts analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables ADS89xxB in achieving high throughput at lower clock speeds, there by simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies the host’s clocking-in of data there by making it ideal for applications involving FPGAs, DSPs. ADS89xxB is compatible with standard SPI Interface.
The ADS89xxB has an internal data parity feature which can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
The ADS8900B, ADS8902B, and ADS8904B (ADS890xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 20-bit successive-approximation-register (SAR) analog-to-digital converters (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS891xB (18-bit) and ADS892xB (16-bit) resolution variants.
The ADS89xxB boosts analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables ADS89xxB in achieving high throughput at lower clock speeds, there by simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies the host’s clocking-in of data there by making it ideal for applications involving FPGAs, DSPs. ADS89xxB is compatible with standard SPI Interface.
The ADS89xxB has an internal data parity feature which can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability. |
ADS8904B20-bit, 250-kSPS, one-channel SAR ADC with internal VREF buffer, internal LDO and enhanced SPI | Integrated Circuits (ICs) | 1 | Active | The ADS8900B, ADS8902B, and ADS8904B (ADS890xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 20-bit successive-approximation-register (SAR) analog-to-digital converters (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS891xB (18-bit) and ADS892xB (16-bit) resolution variants.
The ADS89xxB boosts analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables ADS89xxB in achieving high throughput at lower clock speeds, there by simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies the host’s clocking-in of data there by making it ideal for applications involving FPGAs, DSPs. ADS89xxB is compatible with standard SPI Interface.
The ADS89xxB has an internal data parity feature which can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
The ADS8900B, ADS8902B, and ADS8904B (ADS890xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 20-bit successive-approximation-register (SAR) analog-to-digital converters (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS891xB (18-bit) and ADS892xB (16-bit) resolution variants.
The ADS89xxB boosts analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables ADS89xxB in achieving high throughput at lower clock speeds, there by simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies the host’s clocking-in of data there by making it ideal for applications involving FPGAs, DSPs. ADS89xxB is compatible with standard SPI Interface.
The ADS89xxB has an internal data parity feature which can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability. |
ADS8910B18-Bit, 1-MSPS, 1-Ch SAR ADC with Internal VREF Buffer, Internal LDO and Enhanced SPI Interface | Analog to Digital Converters (ADCs) Evaluation Boards | 3 | Active | The ADS8910B, ADS8912B, and ADS8914B (ADS891xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 18-bit successive approximation register (SAR) analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS892xB (16-bit) resolution variants.
The ADS891xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS891xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
The ADS8910B, ADS8912B, and ADS8914B (ADS891xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 18-bit successive approximation register (SAR) analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS892xB (16-bit) resolution variants.
The ADS891xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS891xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability. |
ADS8912B18-Bit, 500-kSPS, 1-Ch SAR ADC with Internal VREF Buffer, Internal LDO and Enhanced SPI Interface | Data Acquisition | 1 | Active | The ADS8910B, ADS8912B, and ADS8914B (ADS891xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 18-bit successive approximation register (SAR) analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS892xB (16-bit) resolution variants.
The ADS891xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS891xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
The ADS8910B, ADS8912B, and ADS8914B (ADS891xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 18-bit successive approximation register (SAR) analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS892xB (16-bit) resolution variants.
The ADS891xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS891xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability. |
ADS8914B18-Bit, 250-kSPS, 1-Ch SAR ADC with Internal VREF Buffer, Internal LDO and Enhanced SPI Interface | Integrated Circuits (ICs) | 2 | Active | The ADS8910B, ADS8912B, and ADS8914B (ADS891xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 18-bit successive approximation register (SAR) analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS892xB (16-bit) resolution variants.
The ADS891xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS891xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
The ADS8910B, ADS8912B, and ADS8914B (ADS891xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 18-bit successive approximation register (SAR) analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS892xB (16-bit) resolution variants.
The ADS891xB boost analog performance while maintaining high-resolution data transfer by using TI’s enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device an excellent choice for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS891xB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability. |
ADS8920B16-bit, 1-MSPS, one-channel SAR ADC with internal VREF buffer, internal LDO and enhanced SPI | Data Acquisition | 1 | Active | The ADS8920B, ADS8922B, and ADS8924B (ADS892xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 16-bit successive approximation register (SAR) based analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS891xB (18-bit) resolution variants.
The ADS89xxB boost analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device ideal for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS89xxB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
The ADS8920B, ADS8922B, and ADS8924B (ADS892xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 16-bit successive approximation register (SAR) based analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS891xB (18-bit) resolution variants.
The ADS89xxB boost analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device ideal for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS89xxB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability. |
ADS8922B16-bit, 500-kSPS, one-channel SAR ADC with internal VREF buffer, internal LDO and enhanced SPI | Integrated Circuits (ICs) | 1 | Active | The ADS8920B, ADS8922B, and ADS8924B (ADS892xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 16-bit successive approximation register (SAR) based analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS891xB (18-bit) resolution variants.
The ADS89xxB boost analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device ideal for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS89xxB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
The ADS8920B, ADS8922B, and ADS8924B (ADS892xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 16-bit successive approximation register (SAR) based analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS891xB (18-bit) resolution variants.
The ADS89xxB boost analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device ideal for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS89xxB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability. |
ADS8924B16-bit, 250-kSPS, one-channel SAR ADC with internal VREF buffer, internal LDO and enhanced SPI | Analog to Digital Converters (ADC) | 2 | Active | The ADS8920B, ADS8922B, and ADS8924B (ADS892xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 16-bit successive approximation register (SAR) based analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS891xB (18-bit) resolution variants.
The ADS89xxB boost analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device ideal for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS89xxB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.
The ADS8920B, ADS8922B, and ADS8924B (ADS892xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 16-bit successive approximation register (SAR) based analog-to-digital convertors (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS890xB (20-bit) and ADS891xB (18-bit) resolution variants.
The ADS89xxB boost analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables the ADS89xxB to achieve high throughput at lower clock speeds, thereby simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies clocking-in of data, thereby making this device ideal for applications involving FPGAs, DSPs. The ADS89xxB is compatible with a standard SPI Interface.
The ADS89xxB has an internal data parity feature that can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability. |
ADS90010-Bit, 20-MSPS Analog-to-Digital Converter (ADC) | Analog to Digital Converters (ADC) | 3 | Active | The ADS900 is a high-speed pipelined Analog-to-Digital Converter (ADC). This complete converter includes a high bandwidth track-and-hold, a 10-bit quantizer, and an internal reference.
The ADS900 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications.
This high-performance ADC is specified for performance at a 20MHz sampling rate. The ADS900 is available in an SSOP-28 package.
The ADS900 is a high-speed pipelined Analog-to-Digital Converter (ADC). This complete converter includes a high bandwidth track-and-hold, a 10-bit quantizer, and an internal reference.
The ADS900 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications.
This high-performance ADC is specified for performance at a 20MHz sampling rate. The ADS900 is available in an SSOP-28 package. |
ADS90110-Bit, 20-MSPS Analog-to-Digital Converter (ADC) | Analog to Digital Converters (ADC) | 2 | Active | The ADS901 is a high-speed pipelined analog-to-digital converter that operates from a +3V power supply. This complete converter includes a wide bandwidth track/hold and a 10-bit quantizer. The full scale input range is set by external references.
The ADS901 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. The ADS901 is available in an SSOP-28 package.
The ADS901 is a high-speed pipelined analog-to-digital converter that operates from a +3V power supply. This complete converter includes a wide bandwidth track/hold and a 10-bit quantizer. The full scale input range is set by external references.
The ADS901 employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. Its low distortion and high SNR give the extra margin needed for telecommunications, video and test instrumentation applications. The ADS901 is available in an SSOP-28 package. |
