ADS8902B Series

20-bit, 500-kSPS, one-channel SAR ADC with internal VREF buffer, internal LDO and enhanced SPI

Catalog

20-bit, 500-kSPS, one-channel SAR ADC with internal VREF buffer, internal LDO and enhanced SPI

Part	Input Type	Number of Inputs	Data Interface	Ratio - S/H:ADC	Operating Temperature [Max]	Operating Temperature [Min]	Supplier Device Package	Reference Type	Package / Case	Number of Bits	Architecture	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Sampling Rate (Per Second)	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Number of A/D Converters	Configuration	Mounting Type
Texas Instruments ADS8902BRGER	Differential	1	SPI	1:1	125 °C	-40 °C	24-VQFN (4x4)	External Internal	24-VFQFN Exposed Pad	20	SAR	5.5 V	1.65 V	500k	3 V	5.5 V	1	S/H-ADC	Surface Mount
Texas Instruments ADS8902BRGET							24-VQFN (4x4)		24-VFQFN Exposed Pad										Surface Mount

Catalog

20-bit, 500-kSPS, one-channel SAR ADC with internal VREF buffer, internal LDO and enhanced SPI

Key Features

• Resolution: 20-BitsHigh Sample Rate With No Latency Output:ADS8900B: 1-MSPSADS8902B: 500-kSPSADS8904B: 250-kSPSIntegrated LDO Enables Low-Power, Single-Supply OperationLow Power Reference Buffer with No DroopExcellent AC and DC Performance:SNR: 104.5-dB, THD: –125-dBDNL: ±0.2-ppm, 20-Bit No-Missing-CodesINL: ±1-ppmWide Input Range:Unipolar Differential Input Range: ±VREFVREFInput Range: 2.5-V to 5-VEnhanced-SPI Digital InterfaceInterface SCLK : 22-MHz at 1-MSPS.Configurable Data Parity Output.Extended Temperature Range: –40°C to +125°CSmall Footprint: 4-mm × 4-mm VQFNResolution: 20-BitsHigh Sample Rate With No Latency Output:ADS8900B: 1-MSPSADS8902B: 500-kSPSADS8904B: 250-kSPSIntegrated LDO Enables Low-Power, Single-Supply OperationLow Power Reference Buffer with No DroopExcellent AC and DC Performance:SNR: 104.5-dB, THD: –125-dBDNL: ±0.2-ppm, 20-Bit No-Missing-CodesINL: ±1-ppmWide Input Range:Unipolar Differential Input Range: ±VREFVREFInput Range: 2.5-V to 5-VEnhanced-SPI Digital InterfaceInterface SCLK : 22-MHz at 1-MSPS.Configurable Data Parity Output.Extended Temperature Range: –40°C to +125°CSmall Footprint: 4-mm × 4-mm VQFN

Description

The ADS8900B, ADS8902B, and ADS8904B (ADS890xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 20-bit successive-approximation-register (SAR) analog-to-digital converters (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS891xB (18-bit) and ADS892xB (16-bit) resolution variants. The ADS89xxB boosts analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables ADS89xxB in achieving high throughput at lower clock speeds, there by simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies the host’s clocking-in of data there by making it ideal for applications involving FPGAs, DSPs. ADS89xxB is compatible with standard SPI Interface. The ADS89xxB has an internal data parity feature which can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability. The ADS8900B, ADS8902B, and ADS8904B (ADS890xB) belong to a family of pin-to-pin compatible, high-speed, single-channel, high-precision, 20-bit successive-approximation-register (SAR) analog-to-digital converters (ADCs) with an integrated reference buffer and integrated low-dropout regulator (LDO). The device family includes the ADS891xB (18-bit) and ADS892xB (16-bit) resolution variants. The ADS89xxB boosts analog performance while maintaining high-resolution data transfer by using TI’s Enhanced-SPI feature. Enhanced-SPI enables ADS89xxB in achieving high throughput at lower clock speeds, there by simplifying the board layout and lowering system cost. Enhanced-SPI also simplifies the host’s clocking-in of data there by making it ideal for applications involving FPGAs, DSPs. ADS89xxB is compatible with standard SPI Interface. The ADS89xxB has an internal data parity feature which can be appended to the ADC data output. ADC data validation by the host, using parity bits, improves system reliability.