TPS536616-Phase, D-CAP+™ Step-Down VR12.x Server CPU VCORE | Special Purpose Regulators | 1 | Active | 6-Phase, D-CAP+™ Step-Down VR12.x Server CPU VCORE |
| Integrated Circuits (ICs) | 3 | Active | |
| Development Boards, Kits, Programmers | 1 | Active | |
TPS53679Dual-Channel 6+1/5+2 VR13 D-CAP+™ Step-Down Multiphase Controller With NVM and PMBus | Power Management (PMIC) | 2 | Active | The TPS53679 is a fully VR13 SVID compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET ™power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCOREslew rate and voltage positioning round out the Intel®VR13™ features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS53679 device if offered in a thermally enhanced -pin QFN packaged and is rated to operate from –40°C to 125°C.
The TPS53679 is a fully VR13 SVID compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET ™power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCOREslew rate and voltage positioning round out the Intel®VR13™ features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS53679 device if offered in a thermally enhanced -pin QFN packaged and is rated to operate from –40°C to 125°C. |
| Integrated Circuits (ICs) | 3 | Active | |
TPS53685Eight-phase digital step-down multiphase controller with SVI3 and PMBus for AMD platform | Integrated Circuits (ICs) | 1 | Active | The TPS53685 is a fully AMD SVI3 compliant step-down controller with trans-inductor voltage regulator (TLVR) topology support, dual channels, built-in non-volatile memory (NVM), PMBus™ interface, and full compatible with TI NexFET™ smart power stages. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response and good current sharing, minimizing output capacitance requirements. The device also provides a novel phase interleaving strategy and dynamic phase shedding for efficiency improvements at different loads. Adjustable control of VCOREslew rate and voltage positioning work with the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS53685 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C.
The TPS53685 is a fully AMD SVI3 compliant step-down controller with trans-inductor voltage regulator (TLVR) topology support, dual channels, built-in non-volatile memory (NVM), PMBus™ interface, and full compatible with TI NexFET™ smart power stages. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response and good current sharing, minimizing output capacitance requirements. The device also provides a novel phase interleaving strategy and dynamic phase shedding for efficiency improvements at different loads. Adjustable control of VCOREslew rate and voltage positioning work with the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS53685 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C. |
TPS53688Dual-channel, 8 phase step-down, digital multiphase D-CAP+™ controller with VR13.HC SVID and PMBus | Power Management (PMIC) | 2 | Active | Dual-channel, 8 phase step-down, digital multiphase D-CAP+™ controller with VR13.HC SVID and PMBus |
TPS53689Dual-channel, 8 phase step-down, digital multiphase D-CAP+™ controller with VR14 SVID and PMBus | Special Purpose Regulators | 2 | Active | The TPS53689 is a VR14 SVID compliant step down controller with two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stages. Advanced control features such as the D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, low output capacitance, and good dynamic current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.
The TPS53689 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C.
The TPS53689 is a VR14 SVID compliant step down controller with two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stages. Advanced control features such as the D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, low output capacitance, and good dynamic current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.
The TPS53689 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C. |
TPS536C512-phase digital step-down multiphase controller with SVI3 and PMBus for AMD platform | Integrated Circuits (ICs) | 1 | Active | The TPS536C5 is a fully AMD SVI3 compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ smart power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCOREslew rate and voltage positioning round out the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS536C5 device if offered in a thermally enhanced 48-pin QFN packaged and is rated to operate from –40°C to 125°C.
The TPS536C5 is a fully AMD SVI3 compliant step-down controller with dual channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ smart power stage. Advanced control features such as D-CAP+™ architecture with undershoot reduction (USR) provide fast transient response, low output capacitance, and good current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of VCOREslew rate and voltage positioning round out the AMD SVI3 features. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the systems. All programmable parameters can be configured by the PMBus interface and can be stored in NVM as the new default values to minimize the external component count.
The TPS536C5 device if offered in a thermally enhanced 48-pin QFN packaged and is rated to operate from –40°C to 125°C. |
TPS536C7Dual-channel D-CAP+™, PMBus (N+M ≤ 12 phases) step-down, multiphase PWM controller | Integrated Circuits (ICs) | 2 | Active | Dual-channel D-CAP+™, PMBus (N+M ≤ 12 phases) step-down, multiphase PWM controller |
