Texas Instruments

The TPIC44L01, TPIC44L02, and TPIC44L03 are low-side predrivers that provide serial and parallel input interfaces to control four external FET power switches such as offered in the TI TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown is provided on the TPIC44L01/L02. On the TPIC44L03 driver, only over-battery voltage shutdown is provided. Each channel also provides inductive-voltage-transient protection for the external FET. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channels gate output to the external FET. The serial interface is recommended when the number of signals between the control device and the predriver must be minimized and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transition CS\ from high to low to activate the serial input interface. When this occurs, SDO is enabled, fault data is latched into the serial interface, and the fault flag is refreshed. Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must consist of at least four bits of data. In applications where multiple devices are cascaded together, the string of data must consist of four bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for shorted-load and open-load flags (bits 0\x963) for each of the four output channels. A high bit in the fault data indicates a fault and a low bit indicates that no fault is present for that channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault must be present when CS\ is transitioned from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS\ is low. CS\ must be transitioned high after all of the serial data has been clocked into the device. A low-to-high transition of CS\ transfers the last four bits of serial data to the output buffer puts SDO in a high-impedance state and clears and reenables the fault register. The TPIC44L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations. For parallel operation, data is transferred directly from the parallel input interface IN0-IN3 to the respective GATE(0\x963) output asynchronously. SCLK or CS\ is not required for parallel control. A 1 on the parallel input turns the respective channel on, where a 0 turns it off. Note that either the serial input interface or the parallel input interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface. The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied fault-reference voltage through VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault reference when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted fault occurs using the TPIC44L01 or the TPIC44L03, the channel is turned off and a fault flag is sent to the control device as well as to the serial fault register bits. If a fault occurs while using the TPIC44L02, the channel transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load fault conditions must be present for at least the shorted-load deglitch time, t(STBDG), to be flagged as a fault. A fault flag is sent to the control device as well as the serial fault register bits. More detail on fault detection operation is presented in the device operation section of this data sheet. These devices provide protection from over-battery voltage and under-battery voltage conditions irrespective of the state of the output channels. When the battery voltage is greater than the overvoltage threshold or less than the undervoltage threshold, all channels are disabled and a fault flag is generated. Battery-voltage faults are not reported in the serial fault data. The outputs return to normal operation once the battery-voltage fault has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open- and shorted-load conditions. Fault reporting for open- and shorted-load conditions are reenabled after the battery fault condition has been corrected. These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect the FET. The clamp voltage is defined by the sum of VCCand turnon voltage of the external FET. The predriver also provides a gate-to-source voltage (VGS) clamp to protect the gate-source terminals of the power FET from exceeding their rated voltages. An external active low RESET\ is provided to clear all registers and flags in the device. GATE(0\x963) outputs are disabled after RESET\ has been pulled low. These devices provide pulldown resistors on all inputs except CS\ and RESET\. A pullup resistor is used on CS\ and RESET\. The TPIC44L01, TPIC44L02, and TPIC44L03 are low-side predrivers that provide serial and parallel input interfaces to control four external FET power switches such as offered in the TI TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown is provided on the TPIC44L01/L02. On the TPIC44L03 driver, only over-battery voltage shutdown is provided. Each channel also provides inductive-voltage-transient protection for the external FET. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channels gate output to the external FET. The serial interface is recommended when the number of signals between the control device and the predriver must be minimized and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transition CS\ from high to low to activate the serial input interface. When this occurs, SDO is enabled, fault data is latched into the serial interface, and the fault flag is refreshed. Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must consist of at least four bits of data. In applications where multiple devices are cascaded together, the string of data must consist of four bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for shorted-load and open-load flags (bits 0\x963) for each of the four output channels. A high bit in the fault data indicates a fault and a low bit indicates that no fault is present for that channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault must be present when CS\ is transitioned from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS\ is low. CS\ must be transitioned high after all of the serial data has been clocked into the device. A low-to-high transition of CS\ transfers the last four bits of serial data to the output buffer puts SDO in a high-impedance state and clears and reenables the fault register. The TPIC44L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations. For parallel operation, data is transferred directly from the parallel input interface IN0-IN3 to the respective GATE(0\x963) output asynchronously. SCLK or CS\ is not required for parallel control. A 1 on the parallel input turns the respective channel on, where a 0 turns it off. Note that either the serial input interface or the parallel input interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface. The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied fault-reference voltage through VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault reference when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted fault occurs using the TPIC44L01 or the TPIC44L03, the channel is turned off and a fault flag is sent to the control device as well as to the serial fault register bits. If a fault occurs while using the TPIC44L02, the channel transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load fault conditions must be present for at least the shorted-load deglitch time, t(STBDG), to be flagged as a fault. A fault flag is sent to the control device as well as the serial fault register bits. More detail on fault detection operation is presented in the device operation section of this data sheet. These devices provide protection from over-battery voltage and under-battery voltage conditions irrespective of the state of the output channels. When the battery voltage is greater than the overvoltage threshold or less than the undervoltage threshold, all channels are disabled and a fault flag is generated. Battery-voltage faults are not reported in the serial fault data. The outputs return to normal operation once the battery-voltage fault has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open- and shorted-load conditions. Fault reporting for open- and shorted-load conditions are reenabled after the battery fault condition has been corrected. These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect the FET. The clamp voltage is defined by the sum of VCCand turnon voltage of the external FET. The predriver also provides a gate-to-source voltage (VGS) clamp to protect the gate-source terminals of the power FET from exceeding their rated voltages. An external active low RESET\ is provided to clear all registers and flags in the device. GATE(0\x963) outputs are disabled after RESET\ has been pulled low. These devices provide pulldown resistors on all inputs except CS\ and RESET\. A pullup resistor is used on CS\ and RESET\.

The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the Texas Instruments TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown are provided. Battery and output load faults provide real-time fault reporting to the controller. Each channel also provides inductive-voltage-transient protection for the external FET. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channel GATE output to the external FET. The serial input interface is recommended when the number of signals between the control device and the predriver must be minimized, and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transition CS\ from high to low to activate the serial input interface. When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT\ flag is refreshed. Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03), and shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. The fault must be present when CS\ is transitioned from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS\ is low. CS\ must be transitioned high after all of the serial data has been clocked into the device. A low-to-high transition of CS\ transfers the last 6 bits of serial data to the output buffer, puts SDO in a high-impedance state, and clears and reenables the fault register. The TPIC46L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations. For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to the respective GATE output. SCLK or CS\ are not required for parallel control. A 1 on the parallel input turns the respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface. The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT\ as well as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be flagged as a fault. A fault signal is sent to FLT\ as well as the serial fault register bit. More detail on fault detection operation is presented in the device operation section of this data sheet. The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no undervoltage threshold), all channels are disabled and a fault signal is sent to FLT\ as well as to the respective fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are reenabled after the battery fault condition has been corrected. These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect the FET. This clamp voltage is defined by the sum of VCCand turn-on voltage of the external FET. The predriver also provides a gate-to-source voltage (VGS) clamp to protect the GATE-source terminals of the power FET from exceeding their rated voltages. These devices provide pulldown resistors on all inputs except CS\. A pullup resistor is used on CS\. The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the Texas Instruments TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown are provided. Battery and output load faults provide real-time fault reporting to the controller. Each channel also provides inductive-voltage-transient protection for the external FET. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channel GATE output to the external FET. The serial input interface is recommended when the number of signals between the control device and the predriver must be minimized, and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transition CS\ from high to low to activate the serial input interface. When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT\ flag is refreshed. Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03), and shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. The fault must be present when CS\ is transitioned from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS\ is low. CS\ must be transitioned high after all of the serial data has been clocked into the device. A low-to-high transition of CS\ transfers the last 6 bits of serial data to the output buffer, puts SDO in a high-impedance state, and clears and reenables the fault register. The TPIC46L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations. For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to the respective GATE output. SCLK or CS\ are not required for parallel control. A 1 on the parallel input turns the respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface. The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT\ as well as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be flagged as a fault. A fault signal is sent to FLT\ as well as the serial fault register bit. More detail on fault detection operation is presented in the device operation section of this data sheet. The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no undervoltage threshold), all channels are disabled and a fault signal is sent to FLT\ as well as to the respective fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are reenabled after the battery fault condition has been corrected. These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect the FET. This clamp voltage is defined by the sum of VCCand turn-on voltage of the external FET. The predriver also provides a gate-to-source voltage (VGS) clamp to protect the GATE-source terminals of the power FET from exceeding their rated voltages. These devices provide pulldown resistors on all inputs except CS\. A pullup resistor is used on CS\.

The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the Texas Instruments TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown are provided. Battery and output load faults provide real-time fault reporting to the controller. Each channel also provides inductive-voltage-transient protection for the external FET. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channel GATE output to the external FET. The serial input interface is recommended when the number of signals between the control device and the predriver must be minimized, and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transition CS\ from high to low to activate the serial input interface. When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT\ flag is refreshed. Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03), and shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. The fault must be present when CS\ is transitioned from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS\ is low. CS\ must be transitioned high after all of the serial data has been clocked into the device. A low-to-high transition of CS\ transfers the last 6 bits of serial data to the output buffer, puts SDO in a high-impedance state, and clears and reenables the fault register. The TPIC46L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations. For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to the respective GATE output. SCLK or CS\ are not required for parallel control. A 1 on the parallel input turns the respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface. The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT\ as well as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be flagged as a fault. A fault signal is sent to FLT\ as well as the serial fault register bit. More detail on fault detection operation is presented in the device operation section of this data sheet. The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no undervoltage threshold), all channels are disabled and a fault signal is sent to FLT\ as well as to the respective fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are reenabled after the battery fault condition has been corrected. These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect the FET. This clamp voltage is defined by the sum of VCCand turn-on voltage of the external FET. The predriver also provides a gate-to-source voltage (VGS) clamp to protect the GATE-source terminals of the power FET from exceeding their rated voltages. These devices provide pulldown resistors on all inputs except CS\. A pullup resistor is used on CS\. The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the Texas Instruments TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown are provided. Battery and output load faults provide real-time fault reporting to the controller. Each channel also provides inductive-voltage-transient protection for the external FET. These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channel GATE output to the external FET. The serial input interface is recommended when the number of signals between the control device and the predriver must be minimized, and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended. For serial operation, the control device must transition CS\ from high to low to activate the serial input interface. When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT\ flag is refreshed. Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03), and shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. The fault must be present when CS\ is transitioned from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS\ is low. CS\ must be transitioned high after all of the serial data has been clocked into the device. A low-to-high transition of CS\ transfers the last 6 bits of serial data to the output buffer, puts SDO in a high-impedance state, and clears and reenables the fault register. The TPIC46L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations. For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to the respective GATE output. SCLK or CS\ are not required for parallel control. A 1 on the parallel input turns the respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface. The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT\ as well as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel transitions into a low-duty cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be flagged as a fault. A fault signal is sent to FLT\ as well as the serial fault register bit. More detail on fault detection operation is presented in the device operation section of this data sheet. The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no undervoltage threshold), all channels are disabled and a fault signal is sent to FLT\ as well as to the respective fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are reenabled after the battery fault condition has been corrected. These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect the FET. This clamp voltage is defined by the sum of VCCand turn-on voltage of the external FET. The predriver also provides a gate-to-source voltage (VGS) clamp to protect the GATE-source terminals of the power FET from exceeding their rated voltages. These devices provide pulldown resistors on all inputs except CS\. A pullup resistor is used on CS\.

This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multi-functional device capable of storing single-line data in eight addressable latches with 3-to-8 decoding or demultiplexing mode active-low DMOS outputs. Four distinct modes of operation are selectable by controlling the clear (CLR\) and enable (G\) inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS transistor output inverts the data input with all unaddressed DMOS-transistor outputs remaining in their previous states. In the memory mode, all DMOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latch, enable G\ should be held high (inactive) while the address lines are changing. In the 3-to-8 decoding or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are high. In the clear mode, all outputs are high and unaffected by the address and data inputs. Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10, 11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6259 is characterized for operation over the operating case temperature range of -40°C to 125°C. This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multi-functional device capable of storing single-line data in eight addressable latches with 3-to-8 decoding or demultiplexing mode active-low DMOS outputs. Four distinct modes of operation are selectable by controlling the clear (CLR\) and enable (G\) inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS transistor output inverts the data input with all unaddressed DMOS-transistor outputs remaining in their previous states. In the memory mode, all DMOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latch, enable G\ should be held high (inactive) while the address lines are changing. In the 3-to-8 decoding or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are high. In the clear mode, all outputs are high and unaffected by the address and data inputs. Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10, 11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6259 is characterized for operation over the operating case temperature range of -40°C to 125°C.

The TPIC6273 is a monolithic high-voltage high-current power logic octal D-type latch with DMOS transistor outputs designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. The TPIC6273 contains eight positive-edge-triggered D-type flip-flops with a direct clear input. Each flip-flop features an open-drain power DMOS transistor output. When clear (CLR\) is high, information at the D inputs meeting the setup time requirements is transferred to the DRAIN outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input (CLK) is at either the high or low level, the D input signal has no effect at the output. An asynchronous CLR\ is provided to turn all eight DMOS-transistor outputs off. The TPIC6273 is characterized for operation over the operating case temperature range of -40°C to 125°C. The TPIC6273 is a monolithic high-voltage high-current power logic octal D-type latch with DMOS transistor outputs designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. The TPIC6273 contains eight positive-edge-triggered D-type flip-flops with a direct clear input. Each flip-flop features an open-drain power DMOS transistor output. When clear (CLR\) is high, information at the D inputs meeting the setup time requirements is transferred to the DRAIN outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input (CLK) is at either the high or low level, the D input signal has no effect at the output. An asynchronous CLR\ is provided to turn all eight DMOS-transistor outputs off. The TPIC6273 is characterized for operation over the operating case temperature range of -40°C to 125°C.

The TPIC6595 is a monolithic, high-voltage, high-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK) respectively. The storage register transfers data to the output buffer when shift register clear (SRCLR) is high. Write data and read data are valid only when RCK is low. When SRCLR is low, the input shift register is cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. Outputs are low-side, open-drain DMOS transistors with output ratings of 45V and 250mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability. Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1, 10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6595 is characterized for operation over the operating case temperature range of −40°C to 125°C. The TPIC6595 is a monolithic, high-voltage, high-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium-current or high-voltage loads. This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK) respectively. The storage register transfers data to the output buffer when shift register clear (SRCLR) is high. Write data and read data are valid only when RCK is low. When SRCLR is low, the input shift register is cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. The serial output (SER OUT) allows for cascading of the data from the shift register to additional devices. Outputs are low-side, open-drain DMOS transistors with output ratings of 45V and 250mA continuous sink current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high, the DMOS-transistor outputs have sink current capability. Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1, 10, 11, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6595 is characterized for operation over the operating case temperature range of −40°C to 125°C.