Texas Instruments

The TLK4201EA is a versatile, high-speed limiting equalizer for applications in digital high-speed links with data rates up to 4.25 Gbps. This device provides a high-frequency boost of 12 dB at 2.1 GHz as well as sufficient gain to ensure a fully differential output swing for input signals as low as 100 mVP-P(at the input of the interconnect line or cable). The high input signal dynamic range ensures low-jitter output signals even when overdriven with input signal swings as high as 2000 mVP-P. The TLK4201EA includes fixed loss-of-signal (LOS) detection, which can be used to implement a squelch function by connecting the LOS output to the adjacent DISABLE input. The LOS function can be disabled by pulling LOSDIS to high level. The TLK4201EA is available in a small-footprint, 3-mm ×; 3-mm, 16-pin QFN package. It requires a single 3.3-V supply. This very power-efficient equalizer is characterized for operation from -40°C to 85°C. The TLK4201EA is a versatile, high-speed limiting equalizer for applications in digital high-speed links with data rates up to 4.25 Gbps. This device provides a high-frequency boost of 12 dB at 2.1 GHz as well as sufficient gain to ensure a fully differential output swing for input signals as low as 100 mVP-P(at the input of the interconnect line or cable). The high input signal dynamic range ensures low-jitter output signals even when overdriven with input signal swings as high as 2000 mVP-P. The TLK4201EA includes fixed loss-of-signal (LOS) detection, which can be used to implement a squelch function by connecting the LOS output to the adjacent DISABLE input. The LOS function can be disabled by pulling LOSDIS to high level. The TLK4201EA is available in a small-footprint, 3-mm ×; 3-mm, 16-pin QFN package. It requires a single 3.3-V supply. This very power-efficient equalizer is characterized for operation from -40°C to 85°C.

The TLK6002 is a member of a portfolio of multi-gigabit transceivers, intended for use in ultra-high-speed bi-directional point-to-point data transmission systems. It is specifically intended for base station RRH (Remote Radio Head) application, but may also be used in other high speed applications. The TLK6002 supports a serial interface speed of 0.470 Gbps to 6.25 Gbps. Rate support includes all the CPRI and OBSAI rates (0.6144/0.768/1.2288/1.536/2.4576/3.072/4.9152/6.144 Gbps) using a single fixed reference clock frequency (either 122.88 MHz or 153.6 MHz). TLK6002 20-bit parallel interface operates in 1.5V or 1.8V HSTL single-ended format. The 20-bit interface allows low speed signals on the parallel side and therefore enabling the use of low cost FPGA in the system design. The parallel interface can be programmed to be in SDR (Single Data Rate) or DDR (Double Data Rate) modes. The line rate may be set to full (≤6.25Gbps), half (≤3.75Gbps), quarter (≤1.88Gbps) or eighth (≤0.94Gbps). The line rate can be set using either device inputs or software control registers. The TLK6002 performs data conversion parallel-to-serial, serial-to-parallel and clock extraction as a physical layer interface device. The serial transceiver interface operates at a maximum serial data rate of 6.25 Gbps. TLK6002 accepts single-ended HSTL signals at its parallel transmit and receive data buses. If the internal 8B/10B coding and decoding are enabled, TDA/B_[19:0] are latched by TXCLK_A/B and sent to the internal 8b/10b encoder, where the resulting encoded words are serialized and transmitted differentially using a line clock derived from the SERDES reference clock at the desired line rate. If the internal coding and decoding are disabled, TDA/B_[19:0] are defined as 20-bits of data being serialized and transmitted unmodified according to the desired line rate. The receive direction performs the serial-to-parallel conversion on the input serial data synchronizing the resulting 20-bit parallel data to the recovered byte clock (RXCLK_A/B). The optionally decoded receive data is available on the RDA/B_[19:0] output signals. The serial transmitter and receiver are implemented using differential Current Mode Logic (CML) with integrated termination resistors. The TLK6002 provides two local (parallel side) and two remote (serial side) loopback modes for self-test and system diagnostic purposes. The TLK6002 has an integrated loss of signal (LOS) detection function, which is asserted in conditions where the serial input signal does not have sufficient voltage amplitude (≤75 mVdfpp). Note that the input signal must be ≥150 mVdfppwhen loss of signal replacement of the receive datapath data is enabled (register bit 6.6). The TLK6002 is a member of a portfolio of multi-gigabit transceivers, intended for use in ultra-high-speed bi-directional point-to-point data transmission systems. It is specifically intended for base station RRH (Remote Radio Head) application, but may also be used in other high speed applications. The TLK6002 supports a serial interface speed of 0.470 Gbps to 6.25 Gbps. Rate support includes all the CPRI and OBSAI rates (0.6144/0.768/1.2288/1.536/2.4576/3.072/4.9152/6.144 Gbps) using a single fixed reference clock frequency (either 122.88 MHz or 153.6 MHz). TLK6002 20-bit parallel interface operates in 1.5V or 1.8V HSTL single-ended format. The 20-bit interface allows low speed signals on the parallel side and therefore enabling the use of low cost FPGA in the system design. The parallel interface can be programmed to be in SDR (Single Data Rate) or DDR (Double Data Rate) modes. The line rate may be set to full (≤6.25Gbps), half (≤3.75Gbps), quarter (≤1.88Gbps) or eighth (≤0.94Gbps). The line rate can be set using either device inputs or software control registers. The TLK6002 performs data conversion parallel-to-serial, serial-to-parallel and clock extraction as a physical layer interface device. The serial transceiver interface operates at a maximum serial data rate of 6.25 Gbps. TLK6002 accepts single-ended HSTL signals at its parallel transmit and receive data buses. If the internal 8B/10B coding and decoding are enabled, TDA/B_[19:0] are latched by TXCLK_A/B and sent to the internal 8b/10b encoder, where the resulting encoded words are serialized and transmitted differentially using a line clock derived from the SERDES reference clock at the desired line rate. If the internal coding and decoding are disabled, TDA/B_[19:0] are defined as 20-bits of data being serialized and transmitted unmodified according to the desired line rate. The receive direction performs the serial-to-parallel conversion on the input serial data synchronizing the resulting 20-bit parallel data to the recovered byte clock (RXCLK_A/B). The optionally decoded receive data is available on the RDA/B_[19:0] output signals. The serial transmitter and receiver are implemented using differential Current Mode Logic (CML) with integrated termination resistors. The TLK6002 provides two local (parallel side) and two remote (serial side) loopback modes for self-test and system diagnostic purposes. The TLK6002 has an integrated loss of signal (LOS) detection function, which is asserted in conditions where the serial input signal does not have sufficient voltage amplitude (≤75 mVdfpp). Note that the input signal must be ≥150 mVdfppwhen loss of signal replacement of the receive datapath data is enabled (register bit 6.6).

The TLK6201EA is a versatile, high-speed, limiting equalizer for applications in digital high-speed links with data rates up to 6.25 Gbps. This device provides a high-frequency boost of 13 dB on the received data at 3.125 GHz, as well as sufficient gain to ensure a fully differential output swing for input signals as low as 100 mVp-p (at the input of a lossy interconnect line). Four de-emphasis levels can be selected on the transmit side to provide up to 12 dB of additional high-frequency loss compensation. The high input-signal dynamic range ensures low-jitter output signals even when overdriven with input signal swings as high as 2000 mVp-p. The TLK6201EA implements fixed loss-of-signal detection, which can be used to implement a squelch function by connecting the LOS output to the adjacent DIS input. The TLK6201EA is available in a small-footprint, 3-mm × 3-mm, 16-pin QFN package. It requires a single 3.3-V supply. This power-efficient equalizer is characterized for operation from –40°C to 85°C. The TLK6201EA is a versatile, high-speed, limiting equalizer for applications in digital high-speed links with data rates up to 6.25 Gbps. This device provides a high-frequency boost of 13 dB on the received data at 3.125 GHz, as well as sufficient gain to ensure a fully differential output swing for input signals as low as 100 mVp-p (at the input of a lossy interconnect line). Four de-emphasis levels can be selected on the transmit side to provide up to 12 dB of additional high-frequency loss compensation. The high input-signal dynamic range ensures low-jitter output signals even when overdriven with input signal swings as high as 2000 mVp-p. The TLK6201EA implements fixed loss-of-signal detection, which can be used to implement a squelch function by connecting the LOS output to the adjacent DIS input. The TLK6201EA is available in a small-footprint, 3-mm × 3-mm, 16-pin QFN package. It requires a single 3.3-V supply. This power-efficient equalizer is characterized for operation from –40°C to 85°C.

The TLS1233 is a 100-MHz wide-band video preamplifier system intended for mid-to-high-resolution RGB (red-green-blue) color monitors. Each video amplifier (R, G, and B) contains a gain set for adjusting maximum system gain (AV= 7.8 V/V). The TLS1233 provides digital level-operated contrast, brightness, and gain adjustment control. All the control inputs offer high input impedance and an operation range from 0 V to 4 V for easy interface to the serial digital buses. Provided in a 20-pin plastic dual-in-line package (DIP), the TLS1233 integrates most of the external components required to accommodate the video system. The TLS1233 operates from a 12-V supply and contains an internal input bias voltage. Also, the TLS1233 contains the feedback resistor required between output and CLAMP(-) for dc level holding. The device is characterized for operation from 0°C to 70°C. The TLS1233 is a 100-MHz wide-band video preamplifier system intended for mid-to-high-resolution RGB (red-green-blue) color monitors. Each video amplifier (R, G, and B) contains a gain set for adjusting maximum system gain (AV= 7.8 V/V). The TLS1233 provides digital level-operated contrast, brightness, and gain adjustment control. All the control inputs offer high input impedance and an operation range from 0 V to 4 V for easy interface to the serial digital buses. Provided in a 20-pin plastic dual-in-line package (DIP), the TLS1233 integrates most of the external components required to accommodate the video system. The TLS1233 operates from a 12-V supply and contains an internal input bias voltage. Also, the TLS1233 contains the feedback resistor required between output and CLAMP(-) for dc level holding. The device is characterized for operation from 0°C to 70°C.