Texas Instruments

The TLK1101E is a versatile and flexible high-speed equalizer for applications in digital high-speed links with data rates up to 11.3Gbps. The TLK1101E can be configured in many ways to optimize its performance. It provides output de-emphasis adjustable from 0dB to 7dB using pins DE0 and DE1. The output differential voltage swing can be set to 300mVp-p, 600mVp-p, or 900mVp-pusing the SWG pin. A controlling voltage on pin VTH can be used to adjust the input threshold voltage. Pins LN0 and LN1 can be used to optimize the device performance for various interconnect lengths, e.g. from 0 to 20 meters of 24-AWG twinaxial cable. The LOS (loss of signal) assert level can be set to a desired level through a controlling voltage connected to pin LOSL. The LOS assert levels can be chosen from two LOS assert level ranges selectable with the LOSR pin. The output can be disabled using the DIS pin. The DIS and the LOS pin can be connected together to implement a squelch function. The de-emphasis, the output voltage swing, the input threshold voltage, the output disable, and the LOS assert levels and ranges can alternatively be set using the two-wire serial interface through the SCL and SDA pins. The external pin configuration is the default device setup method. The active device control method is selected through register address 0 bit 0 (see Table 4 and Table 20). The two-wire serial interface also allows for the control of the input bandwidth to optimize the device performance for various data rates. The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1600mVp-pdifferential. The low-frequency cut-off is low enough to support low-frequency control signals such as SAS and SATA out-of-band (OOB) signals. The TLK1101E is a versatile and flexible high-speed equalizer for applications in digital high-speed links with data rates up to 11.3Gbps. The TLK1101E can be configured in many ways to optimize its performance. It provides output de-emphasis adjustable from 0dB to 7dB using pins DE0 and DE1. The output differential voltage swing can be set to 300mVp-p, 600mVp-p, or 900mVp-pusing the SWG pin. A controlling voltage on pin VTH can be used to adjust the input threshold voltage. Pins LN0 and LN1 can be used to optimize the device performance for various interconnect lengths, e.g. from 0 to 20 meters of 24-AWG twinaxial cable. The LOS (loss of signal) assert level can be set to a desired level through a controlling voltage connected to pin LOSL. The LOS assert levels can be chosen from two LOS assert level ranges selectable with the LOSR pin. The output can be disabled using the DIS pin. The DIS and the LOS pin can be connected together to implement a squelch function. The de-emphasis, the output voltage swing, the input threshold voltage, the output disable, and the LOS assert levels and ranges can alternatively be set using the two-wire serial interface through the SCL and SDA pins. The external pin configuration is the default device setup method. The active device control method is selected through register address 0 bit 0 (see Table 4 and Table 20). The two-wire serial interface also allows for the control of the input bandwidth to optimize the device performance for various data rates. The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1600mVp-pdifferential. The low-frequency cut-off is low enough to support low-frequency control signals such as SAS and SATA out-of-band (OOB) signals.

The TLK1102E is a versatile and flexible high-speed dual-channel equalizer for applications in digital high-speed links with data rates up to 11.3Gbps. The TLK1102E can be configured in many ways through its two-wire serial interface, available through the SDA and the SCL pins, to optimize its performance. The configurable parameters include the output de-emphasis settable from 0 to 7dB, the output differential voltage swing settable from 225 to 1200mVp-p, the input equalization level settable for 0 to 20 meters of 24-AWG twinaxial cable, 0 to 40 inches of FR-4 PCB interconnect, or equivalent interconnect, the input filter bandwidth settable from 4.5 to 11GHz, and the LOS (loss of signal) assert voltage level. Alternatively, the TLK1102E can be configured using its configuration pins in two modes selectable using the MODE pin. In Pin Control Mode 1, a common setting can be set for the two channels for the output de-emphasis level and the interconnect length using the DE pin and LN0, LN1 pins respectively. In Pin Control Mode 2, those parameters can be set individually for the two channels using DEA, DEB, LNA, and LNB pins. In both modes only a common setting is available for the output voltage swing using the SWG pin. For Pin Control Mode 2 the typical LOS assert and de-assert voltage levels are fixed at 90mVp-pand 150mVp-prespectively with 4.0dB hysteresis. The outputs can be disabled using the DISA and DISB pins. The DISA/DISB pins and the LOSA/LOSB pins can be connected together to implement an external output squelch function. The TLK1102E implements an internal output squelch function that can be enabled using the two-wire serial interface. In addition, a special fast auto-squelch function can be selected through the two-wire serial interface when needed to support SAS and SATA out-of-band (OOB) signals. The POLA and POLB pins can be used to reverse the polarity of the OUTA+/OUTA- and OUTB+/OUTB- pins respectively. The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1600mVp-pdifferential. The low-frequency cut-off is low enough to support low-frequency control signals such as SAS and SATA OOB signals. The loss-of-signal detection and output disable functions are carefully designed to meet SAS/SATA OOB signal timing constraints. The TLK1102E is a versatile and flexible high-speed dual-channel equalizer for applications in digital high-speed links with data rates up to 11.3Gbps. The TLK1102E can be configured in many ways through its two-wire serial interface, available through the SDA and the SCL pins, to optimize its performance. The configurable parameters include the output de-emphasis settable from 0 to 7dB, the output differential voltage swing settable from 225 to 1200mVp-p, the input equalization level settable for 0 to 20 meters of 24-AWG twinaxial cable, 0 to 40 inches of FR-4 PCB interconnect, or equivalent interconnect, the input filter bandwidth settable from 4.5 to 11GHz, and the LOS (loss of signal) assert voltage level. Alternatively, the TLK1102E can be configured using its configuration pins in two modes selectable using the MODE pin. In Pin Control Mode 1, a common setting can be set for the two channels for the output de-emphasis level and the interconnect length using the DE pin and LN0, LN1 pins respectively. In Pin Control Mode 2, those parameters can be set individually for the two channels using DEA, DEB, LNA, and LNB pins. In both modes only a common setting is available for the output voltage swing using the SWG pin. For Pin Control Mode 2 the typical LOS assert and de-assert voltage levels are fixed at 90mVp-pand 150mVp-prespectively with 4.0dB hysteresis. The outputs can be disabled using the DISA and DISB pins. The DISA/DISB pins and the LOSA/LOSB pins can be connected together to implement an external output squelch function. The TLK1102E implements an internal output squelch function that can be enabled using the two-wire serial interface. In addition, a special fast auto-squelch function can be selected through the two-wire serial interface when needed to support SAS and SATA out-of-band (OOB) signals. The POLA and POLB pins can be used to reverse the polarity of the OUTA+/OUTA- and OUTB+/OUTB- pins respectively. The high input signal dynamic range ensures low jitter output signals even when overdriven with input signal swings as high as 1600mVp-pdifferential. The low-frequency cut-off is low enough to support low-frequency control signals such as SAS and SATA OOB signals. The loss-of-signal detection and output disable functions are carefully designed to meet SAS/SATA OOB signal timing constraints.

The TLK111 is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling. This device integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. The TLK111 supports the standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) for direct connection to a Media Access Controller (MAC). The TLK111 is designed for power-supply flexibility, and can operate with a single 3.3V power supply or with combinations of 3.3V and 1.55V power supplies for reduced power operation. The TLK111 uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT 5 twisted-pair wiring. This device not only meets the requirements of IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise. The TLK111 Ethernet PHY has a special Power Back Off mode to conserve power in systems with relatively short cables. This mode provides the flexibility to reduce system power when the system is not required to drive the standard IEEE 802.3 100m cable length, or the extended 150m, error-free cable reach of the TLK111. For more detail, see application note SLLA328. The TLK111 is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling. This device integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. The TLK111 supports the standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) for direct connection to a Media Access Controller (MAC). The TLK111 is designed for power-supply flexibility, and can operate with a single 3.3V power supply or with combinations of 3.3V and 1.55V power supplies for reduced power operation. The TLK111 uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT 5 twisted-pair wiring. This device not only meets the requirements of IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise. The TLK111 Ethernet PHY has a special Power Back Off mode to conserve power in systems with relatively short cables. This mode provides the flexibility to reduce system power when the system is not required to drive the standard IEEE 802.3 100m cable length, or the extended 150m, error-free cable reach of the TLK111. For more detail, see application note SLLA328.

The TLK1501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK1501 supports an effective serial interface speed of 0.6 Gbps to 1.5 Gbps, providing up to 1.2 Gbps of data bandwidth. The TLK1501 is pin-for-pin compatible with the TLK2500. The TLK1501 is both pin-for-pin compatible with and functionally identical to the TLK2501, a 1.6 to 2.5 Gbps transceiver, and the TLK3101, a 2.5 to 3.125 Gbps transceiver, providing a wide range of performance solutions with no required board layout changes. The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50. The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future. The TLK1501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.5 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 480 Mbps to 1.2 Gbps (16 bits data x the GTX_CLK frequency). The TLK1501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK1501 PowerPAD be soldered to the thermal land on the board. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board. The TLK1501 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface. The TLK1501 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low during power up. This circuit also holds the parallel side output signal terminals during power up as well as DOUTTXP and DOUTTXN in a high-impedance state. The TLK1501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock. To prevent a data bit error from causing a valid data packet from being interpreted as a comma and thus causing the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in TLK1501. The TLK1501 allows users to implement redundant ports by connecting receive data bus terminals from two TLK1501 devices together. Asserting the LCKREFN to a low state causes the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a transmit-only mode, since the receiver is not tracking the data. The TLK1501 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power-efficient, consuming less than 360 mW typically. The TLK1501 is characterized for operation from –40°C to 85°C. The TLK1501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK1501 supports an effective serial interface speed of 0.6 Gbps to 1.5 Gbps, providing up to 1.2 Gbps of data bandwidth. The TLK1501 is pin-for-pin compatible with the TLK2500. The TLK1501 is both pin-for-pin compatible with and functionally identical to the TLK2501, a 1.6 to 2.5 Gbps transceiver, and the TLK3101, a 2.5 to 3.125 Gbps transceiver, providing a wide range of performance solutions with no required board layout changes. The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50. The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future. The TLK1501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.5 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 480 Mbps to 1.2 Gbps (16 bits data x the GTX_CLK frequency). The TLK1501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK1501 PowerPAD be soldered to the thermal land on the board. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board. The TLK1501 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface. The TLK1501 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low during power up. This circuit also holds the parallel side output signal terminals during power up as well as DOUTTXP and DOUTTXN in a high-impedance state. The TLK1501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock. To prevent a data bit error from causing a valid data packet from being interpreted as a comma and thus causing the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in TLK1501. The TLK1501 allows users to implement redundant ports by connecting receive data bus terminals from two TLK1501 devices together. Asserting the LCKREFN to a low state causes the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a transmit-only mode, since the receiver is not tracking the data. The TLK1501 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power-efficient, consuming less than 360 mW typically. The TLK1501 is characterized for operation from –40°C to 85°C.

The TLK2201B and TLK2201BI gigabit ethernet transceivers provide for ultrahigh-speed full-duplex point-to-point data transmissions. These devices are based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 Gigabit Ethernet specification. The TLK2201B supports data rates from 1.0 Gbps through 1.6 Gbps and the TLK2201BI supports data rates from 1.2 Gbps through 1.6 Gbps. The primary application of these devices is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50. The transmission media can be printed-circuit board traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The TLK2201B and TLK2201BI perform the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface. The TLK2201B and TLK2201BI support both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned to both the rising and falling edge of the reference clock. The data is clocked most significant bit first, (bits 0-4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5-9 of the 8b/10b encoded data) are clocked on the falling edge of the clock. The TLK2201B and TLK2201BI provide a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported. The TLK2201B and TLK2201BI are housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK2201B and TLK2201BI PowerPADs be soldered to the thermal land on the board. The TLK2201B is characterized for operation from 0°C to 70°C. The TLK2201BI is characterized for operation from -40°C to 85°C. The TLK2201B and TLK2201BI use a 2.5-V supply. The I/O section is 3.3-V compatible. With the 2.5-V supply the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps. The TLK2201B and TLK2201BI are designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in high-impedance state. The TLK2201B and TLK2201BI gigabit ethernet transceivers provide for ultrahigh-speed full-duplex point-to-point data transmissions. These devices are based on the timing requirements of the 10-bit interface specification by the IEEE 802.3 Gigabit Ethernet specification. The TLK2201B supports data rates from 1.0 Gbps through 1.6 Gbps and the TLK2201BI supports data rates from 1.2 Gbps through 1.6 Gbps. The primary application of these devices is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50. The transmission media can be printed-circuit board traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The TLK2201B and TLK2201BI perform the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface. The TLK2201B and TLK2201BI support both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte. In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned to both the rising and falling edge of the reference clock. The data is clocked most significant bit first, (bits 0-4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5-9 of the 8b/10b encoded data) are clocked on the falling edge of the clock. The TLK2201B and TLK2201BI provide a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported. The TLK2201B and TLK2201BI are housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK2201B and TLK2201BI PowerPADs be soldered to the thermal land on the board. The TLK2201B is characterized for operation from 0°C to 70°C. The TLK2201BI is characterized for operation from -40°C to 85°C. The TLK2201B and TLK2201BI use a 2.5-V supply. The I/O section is 3.3-V compatible. With the 2.5-V supply the chipset is very power-efficient, dissipating less than 200 mW typical power when operating at 1.25 Gbps. The TLK2201B and TLK2201BI are designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in high-impedance state.