Texas Instruments

This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. When VCCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. When VCCis between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT244B is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT244B is organized as two 4-bit line drivers with separate output-enable (OE)\ inputs. When OE\ is low, the device passes data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

This octal bus transceiver is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT245B is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. This octal bus transceiver is designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The SN74LVT245B is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

These octal transceivers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The 'LVT543 contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (or) and output-enable(or) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable () input must be low in order to enter data from A or to output data from B. Ifis low andis low, the A-to-B latches are transparent; a subsequent low-to-high transition ofputs the A latches in the storage mode. Withandboth low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the,, andinputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT543 is characterized for operation from -40°C to 85°C. These octal transceivers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The 'LVT543 contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (or) and output-enable(or) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable () input must be low in order to enter data from A or to output data from B. Ifis low andis low, the A-to-B latches are transparent; a subsequent low-to-high transition ofputs the A latches in the storage mode. Withandboth low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the,, andinputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT543 is characterized for operation from -40°C to 85°C.

These octal latches are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The eight latches of the 'LVT573 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT573 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT573 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT573 is characterized for operation from -40°C to 85°C. These octal latches are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The eight latches of the 'LVT573 are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT573 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT573 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT573 is characterized for operation from -40°C to 85°C.

These octal flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the ´LVT574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT574 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT574 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT574 is characterized for operation from -40°C to 85°C. These octal flip-flops are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The eight flip-flops of the ´LVT574 are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enableinput can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components.does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT574 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT574 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT574 is characterized for operation from -40°C to 85°C.

The ’LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and configuration/maintenance facilities at board and system levels. The eTBCs master all TAP signals required to support one 4- or 5-wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and test reset (TRST)\. All such signals can be connected directly to the associated target IEEE Std 1149.1 devices without need for additional logic or buffering. However, as well as being directly connected, the TMS, TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a pipeline, with a retiming delay of up to 15 TCK cycles; the eTBCs automatically handle all associated serial-data justification. Conceptually, the eTBCs operate as simple 8-bit memory- or I/O-mapped peripherals to a microprocessor/microcontroller (host). High-level commands and parallel data are passed to/from the eTBCs via their generic host interface, which includes an 8-bit data bus (D7–D0) and a 3-bit address bus (A2–A0). Read/write select (R/W\) and strobe (STRB)\ signals are implemented so that the critical host-interface timing is independent of the CLKIN period. An asynchronous ready (RDY) indicator is provided to hold off, or insert wait states into, a host read/write cycle when the eTBCs cannot respond immediately to the requested read/write operation. High-level commands are issued by the host to cause the eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state to any other such stable state, to scan instruction or data through test registers in target devices, and/or to execute instructions in the Run-Test/Idle TAP state. A 32-bit counter can be programmed to allow a predetermined number of scan or execute cycles. During scan operations, serial data that appears at the TDI input is transferred into a serial to 4 × 8-bit-parallel first-in/first-out (FIFO) read buffer, which can then be read by the host to obtain the return serial-data stream up to eight bits at a time. Serial data that is to be transmitted from the TDO output is written by the host, up to eight bits at a time, to a 4 × 8-bit-parallel to serial FIFO write buffer. In addition to such simple state-movement, scan, and run-test operations, the eTBCs support several additional commands that provide for input-only scans, output-only scans, recirculate scans (in which TDI is mirrored back to TDO), and a scan mode that generates the protocols used to support multidrop TAP configurations using TI’s addressable scan port. Two loopback modes also are supported that allow the microprocessor/microcontroller host to monitor the TDO or TMS data streams output by the eTBCs. The eTBCs’ flexible clocking architecture allows the user to choose between free-running (in which the TCK always follows CLKIN) and gated modes (in which the TCK output is held static except during state-move, run-test, or scan cycles) as well as to divide down TCK from CLKIN. A discrete mode also is available in which the TAP is driven strictly by read/write cycles under full control of the microprocessor/microcontroller host. These features ensure that virtually any IEEE Std 1149.1 target device or device chain can be serviced by the eTBCs, even where such may not fully comply to IEEE Std 1149.1 While most operations of the eTBCs are synchronous to CLKIN, a test-output enable (TOE)\ is provided for output control of the TAP outputs, and a reset (RST)\ input is provided for hardware reset of the eTBCs. The former can be used to disable the eTBCs so that an external controller can master the associated IEEE Std 1149.1 test bus. The ’LVT8980A embedded test-bus controllers (eTBCs) are members of the TI broad family of testability integrated circuits. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most other devices of this family, the eTBCs are not boundary-scannable devices; rather, their function is to master an IEEE Std 1149.1 (JTAG) test access port (TAP) under the command of an embedded host microprocessor/microcontroller. Thus, the eTBCs enable the practical and effective use of the IEEE Std 1149.1 test-access infrastructure to support embedded/built-in test, emulation, and configuration/maintenance facilities at board and system levels. The eTBCs master all TAP signals required to support one 4- or 5-wire IEEE Std 1149.1 serial test bus: test clock (TCK), test mode select (TMS), test data input (TDI), test data output (TDO), and test reset (TRST)\. All such signals can be connected directly to the associated target IEEE Std 1149.1 devices without need for additional logic or buffering. However, as well as being directly connected, the TMS, TDI, and TDO signals can be connected to distant target IEEE Std 1149.1 devices via a pipeline, with a retiming delay of up to 15 TCK cycles; the eTBCs automatically handle all associated serial-data justification. Conceptually, the eTBCs operate as simple 8-bit memory- or I/O-mapped peripherals to a microprocessor/microcontroller (host). High-level commands and parallel data are passed to/from the eTBCs via their generic host interface, which includes an 8-bit data bus (D7–D0) and a 3-bit address bus (A2–A0). Read/write select (R/W\) and strobe (STRB)\ signals are implemented so that the critical host-interface timing is independent of the CLKIN period. An asynchronous ready (RDY) indicator is provided to hold off, or insert wait states into, a host read/write cycle when the eTBCs cannot respond immediately to the requested read/write operation. High-level commands are issued by the host to cause the eTBCs to generate the TMS sequences necessary to move the test bus from any stable TAP-controller state to any other such stable state, to scan instruction or data through test registers in target devices, and/or to execute instructions in the Run-Test/Idle TAP state. A 32-bit counter can be programmed to allow a predetermined number of scan or execute cycles. During scan operations, serial data that appears at the TDI input is transferred into a serial to 4 × 8-bit-parallel first-in/first-out (FIFO) read buffer, which can then be read by the host to obtain the return serial-data stream up to eight bits at a time. Serial data that is to be transmitted from the TDO output is written by the host, up to eight bits at a time, to a 4 × 8-bit-parallel to serial FIFO write buffer. In addition to such simple state-movement, scan, and run-test operations, the eTBCs support several additional commands that provide for input-only scans, output-only scans, recirculate scans (in which TDI is mirrored back to TDO), and a scan mode that generates the protocols used to support multidrop TAP configurations using TI’s addressable scan port. Two loopback modes also are supported that allow the microprocessor/microcontroller host to monitor the TDO or TMS data streams output by the eTBCs. The eTBCs’ flexible clocking architecture allows the user to choose between free-running (in which the TCK always follows CLKIN) and gated modes (in which the TCK output is held static except during state-move, run-test, or scan cycles) as well as to divide down TCK from CLKIN. A discrete mode also is available in which the TAP is driven strictly by read/write cycles under full control of the microprocessor/microcontroller host. These features ensure that virtually any IEEE Std 1149.1 target device or device chain can be serviced by the eTBCs, even where such may not fully comply to IEEE Std 1149.1 While most operations of the eTBCs are synchronous to CLKIN, a test-output enable (TOE)\ is provided for output control of the TAP outputs, and a reset (RST)\ input is provided for hardware reset of the eTBCs. The former can be used to disable the eTBCs so that an external controller can master the associated IEEE Std 1149.1 test bus.

The 'LVT8986 linking addressable scan ports (LASPs) are members of the TI family of IEEE Std 1149.1 (JTAG) scan-support products. The scan-support product family facilitates testing of fully boundary-scannable devices. The LASP applies linking shadow protocols through the test access port (TAP) to extend scan access to the system level and divide scan chains at the board level. The LASP consists of a primary TAP for interfacing to the backplane IEEE Std 1149.1 serial-bus signals (PTDI, PTMS, PTCK, PTDO,PRTST) and three secondary TAPs for interfacing to the board-level IEEE Std 1149.1 serial-bus signals. Each secondary TAP consists of signals STDIx, STMSx, STCKx, STDOx, andSTRSTx. Conceptually, the LASP is a gateway device that can be used to connect a set of primary TAP signals to a set of secondary TAP signals — for example, to interface backplane TAP signals to a board-level TAP. The LASP provides all signal buffering that might be required at these two interfaces. Primary-to-secondary TAP connections can be configured with the help of linking shadow protocol or protocol bypass (BYP5-BYP0) inputs. Most operations of the LASP are synchronous to the primary test clock (PTCK) input. PTCK always is buffered directly onto the secondary test clock (STCK2-STCK0) outputs. Upon power up of the device, the LASP assumes a condition in which the primary TAP is disconnected from the secondary TAPs (unless the bypass signals are used, as shown in Function Tables 1 and 2). This reset condition also can be entered by asserting the primary test reset (PTRST) input or by using the linking shadow protocol.PTRSTalways is buffered directly onto the secondary test reset (STRST2-STRST0) outputs, ensuring that the LASP and its associated secondary TAPs can be reset simultaneously. The primary test data output (PTDO) can be configured to receive secondary test data inputs (STDI2-STDI0). Secondary test data outputs (STDO2-STDO0) can be configured to receive either the primary test data input (PTDI), STDI2-STDI0, or the cascade test data input (CTDI). Cascade test data output (CTDO) can be configured to receive either of STDI2-STDI0, or CTDI. CTDI and CTDO facilitate cascading multiple LASPs, which is explained in the latter part of this section. Similarly, secondary test-mode select (STMS2-STMS0) outputs can be configured to receive the primary test-mode select (PTMS) input. When any secondary TAP is disconnected, its respective STDO is at high impedance. Upon disconnecting the secondary TAP, the corresponding STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state. The address (A9-A0) inputs to the LASP are used to identify the LASP. The position (P2-P0) inputs to the LASP are used to identify the position of the LASP within a cascade chain when multiple LASPs are cascaded. Up to 8 LASPs can be cascaded to link a maximum of 24 secondary scan paths to 1 primary scan path. In a system, primary-to-secondary connection is based on linking shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states, other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address, position the LASP in the cascade chain that is being configured, and configuration of secondary TAPs via a serial bit-pair signaling scheme. When address and position bits received serially at PTDI match those at the parallel address (A9-A0) inputs and position (P2-P0) inputs respectively, the secondary TAPs are configured per the configuration bits received during the linking shadow protocol, then LASP serially retransmits the entire linking shadow protocol as an acknowledgment and assumes the connected (ON) status. If the received address or position does not match that at the address (A9-A0) inputs or position (P2-P0) inputs, the LASP immediately assumes the disconnected (OFF) status, without acknowledgment. The LASP also supports three dedicated addresses that can be received globally (that is, to which all LASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the LASP to disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving LASPs. The DSA is especially useful when the secondary TAPs of multiple LASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the LASP to assume the reset condition. Receipt of the test-synchronization address (TSA) causes the LASP to assume a connect status (MULTICAST) in which PTDO is at high impedance, but the configuration of the secondary TAPs are maintained to allow simultaneous operation of the secondary TAPs of multiple LASPs. This is useful for multicast TAP-state movement, simultaneous test operation, such as in Run-Test/Idle state, and scanning of common test data into multiple like scan chains. The MULTICAST status may also be useful for concurrent in-system programming (ISP) of common modules. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states. Refer to Table 9 for different address mapping. Alternatively, primary-to-secondary connection can be selected by asserting a low level at the bypass (BYP5) input. The remaining bypass (BYP4-BYP0) inputs are used for configuring the secondary TAPs. This operation is asynchronous to PTCK and is independent of PTRST and/or power-up reset. This bypassing feature is especially useful in the board-test environment because it allows board-level automated test equipment (ATE) to treat the LASP as a simple transceiver. WhenBYP5is high, the LASP is free to respond to linking shadow protocols. Otherwise, whenBYP5is low, linking shadow protocols are ignored. Whether the connected status is achieved by use of linking shadow protocol or by use of bypass inputs, this status is indicated by a low level at the connect (CON2-CON0) outputs. Likewise, when the secondary TAP is disconnected from the primary TAP, the correspondingCONoutput is high. Each secondary TAP has a pass-through input and output consisting of SX2-SX0and SY2-SY0, respectively. Similarly, the primary TAP also has a pass-through input and output consisting of PX and PY, respectively. Pass-through input PX drives the SY outputs of the secondary TAPs that are connected to the primary TAP. Disconnected secondary TAPs have their SY outputs at high impedance. Pass-through inputs SY2-SY0of the connected secondary TAPs are logically ANDed and drive the PY output. The 'LVT8986 linking addressable scan ports (LASPs) are members of the TI family of IEEE Std 1149.1 (JTAG) scan-support products. The scan-support product family facilitates testing of fully boundary-scannable devices. The LASP applies linking shadow protocols through the test access port (TAP) to extend scan access to the system level and divide scan chains at the board level. The LASP consists of a primary TAP for interfacing to the backplane IEEE Std 1149.1 serial-bus signals (PTDI, PTMS, PTCK, PTDO,PRTST) and three secondary TAPs for interfacing to the board-level IEEE Std 1149.1 serial-bus signals. Each secondary TAP consists of signals STDIx, STMSx, STCKx, STDOx, andSTRSTx. Conceptually, the LASP is a gateway device that can be used to connect a set of primary TAP signals to a set of secondary TAP signals — for example, to interface backplane TAP signals to a board-level TAP. The LASP provides all signal buffering that might be required at these two interfaces. Primary-to-secondary TAP connections can be configured with the help of linking shadow protocol or protocol bypass (BYP5-BYP0) inputs. Most operations of the LASP are synchronous to the primary test clock (PTCK) input. PTCK always is buffered directly onto the secondary test clock (STCK2-STCK0) outputs. Upon power up of the device, the LASP assumes a condition in which the primary TAP is disconnected from the secondary TAPs (unless the bypass signals are used, as shown in Function Tables 1 and 2). This reset condition also can be entered by asserting the primary test reset (PTRST) input or by using the linking shadow protocol.PTRSTalways is buffered directly onto the secondary test reset (STRST2-STRST0) outputs, ensuring that the LASP and its associated secondary TAPs can be reset simultaneously. The primary test data output (PTDO) can be configured to receive secondary test data inputs (STDI2-STDI0). Secondary test data outputs (STDO2-STDO0) can be configured to receive either the primary test data input (PTDI), STDI2-STDI0, or the cascade test data input (CTDI). Cascade test data output (CTDO) can be configured to receive either of STDI2-STDI0, or CTDI. CTDI and CTDO facilitate cascading multiple LASPs, which is explained in the latter part of this section. Similarly, secondary test-mode select (STMS2-STMS0) outputs can be configured to receive the primary test-mode select (PTMS) input. When any secondary TAP is disconnected, its respective STDO is at high impedance. Upon disconnecting the secondary TAP, the corresponding STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state. The address (A9-A0) inputs to the LASP are used to identify the LASP. The position (P2-P0) inputs to the LASP are used to identify the position of the LASP within a cascade chain when multiple LASPs are cascaded. Up to 8 LASPs can be cascaded to link a maximum of 24 secondary scan paths to 1 primary scan path. In a system, primary-to-secondary connection is based on linking shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states, other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address, position the LASP in the cascade chain that is being configured, and configuration of secondary TAPs via a serial bit-pair signaling scheme. When address and position bits received serially at PTDI match those at the parallel address (A9-A0) inputs and position (P2-P0) inputs respectively, the secondary TAPs are configured per the configuration bits received during the linking shadow protocol, then LASP serially retransmits the entire linking shadow protocol as an acknowledgment and assumes the connected (ON) status. If the received address or position does not match that at the address (A9-A0) inputs or position (P2-P0) inputs, the LASP immediately assumes the disconnected (OFF) status, without acknowledgment. The LASP also supports three dedicated addresses that can be received globally (that is, to which all LASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the LASP to disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving LASPs. The DSA is especially useful when the secondary TAPs of multiple LASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the LASP to assume the reset condition. Receipt of the test-synchronization address (TSA) causes the LASP to assume a connect status (MULTICAST) in which PTDO is at high impedance, but the configuration of the secondary TAPs are maintained to allow simultaneous operation of the secondary TAPs of multiple LASPs. This is useful for multicast TAP-state movement, simultaneous test operation, such as in Run-Test/Idle state, and scanning of common test data into multiple like scan chains. The MULTICAST status may also be useful for concurrent in-system programming (ISP) of common modules. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states. Refer to Table 9 for different address mapping. Alternatively, primary-to-secondary connection can be selected by asserting a low level at the bypass (BYP5) input. The remaining bypass (BYP4-BYP0) inputs are used for configuring the secondary TAPs. This operation is asynchronous to PTCK and is independent of PTRST and/or power-up reset. This bypassing feature is especially useful in the board-test environment because it allows board-level automated test equipment (ATE) to treat the LASP as a simple transceiver. WhenBYP5is high, the LASP is free to respond to linking shadow protocols. Otherwise, whenBYP5is low, linking shadow protocols are ignored. Whether the connected status is achieved by use of linking shadow protocol or by use of bypass inputs, this status is indicated by a low level at the connect (CON2-CON0) outputs. Likewise, when the secondary TAP is disconnected from the primary TAP, the correspondingCONoutput is high. Each secondary TAP has a pass-through input and output consisting of SX2-SX0and SY2-SY0, respectively. Similarly, the primary TAP also has a pass-through input and output consisting of PX and PY, respectively. Pass-through input PX drives the SY outputs of the secondary TAPs that are connected to the primary TAP. Disconnected secondary TAPs have their SY outputs at high impedance. Pass-through inputs SY2-SY0of the connected secondary TAPs are logically ANDed and drive the PY output.

The 'LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETMdevices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level. These devices are functionally equivalent to the 'ABT8996 ASPs. Additionally, they are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to interface to 5-V masters and/or targets. Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are connected, only a moderate propagation delay is introduced - no storage/retiming elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use. Most operations of the ASP are synchronous to the primary test clock (PTCK) input. PTCK is always buffered directly onto the secondary test clock (STCK) output. Upon power up of the device, the ASP assumes a condition in which the primary TAP is disconnected from the secondary TAP (unless the bypass signal is used, as below). This reset condition also can be entered by the assertion of the primary test reset (PTRST\) input or by use of shadow protocol. PTRST\ is always buffered directly onto the secondary test reset (STRST\) output, ensuring that the ASP and its associated secondary TAP can be reset simultaneously. When connected, the primary test data input (PTDI) and primary test mode select (PTMS) input are buffered onto the secondary test data output (STDO) and secondary test mode select (STMS) output, respectively, while the secondary test data input (STDI) is buffered onto the primary test data output (PTDO). When disconnected, STDO is at high impedance, while PTDO is at high impedance, except during acknowledgment of a shadow protocol. Upon disconnect of the secondary TAP, STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state. Upon reset of the ASP, STMS is high, allowing the secondary TAP to be synchronously reset to the Test-Logic-Reset state. In system, primary-to-secondary connection is based on shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address via a serial bit-pair signaling scheme. When an address is received serially at PTDI that matches that at the parallel address inputs (A9-A0), the ASP serially retransmits its address at PTDO as an acknowledgment and then assumes the connected (ON) status, as above. If the received address does not match that at the address inputs, the ASP immediately assumes the disconnected (OFF) status without acknowledgment. The ASP also supports three dedicated addresses that can be received globally (that is, to which all ASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the ASP to disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving ASPs. The DSA is especially useful when the secondary TAPs of multiple ASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the ASP to assume the reset condition, as above. Receipt of the test-synchronization address (TSA) causes the ASP to assume a connect status (MULTICAST) in which PTDO is at high impedance but the connections from PTMS to STMS and PTDI to STDO are maintained to allow simultaneous operation of the secondary TAPs of multiple ASPs. This is useful for multicast TAP-state movement, simultaneous test operation (such as in Run-Test/Idle state), and scanning of common test data into multiple like scan chains. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states. Alternatively, primary-to-secondary connection can be selected by assertion of a low level at the bypass (BYP\) input. This operation is asynchronous to PTCK and is independent of PTRST\ and/or power-up reset. This bypassing feature is especially useful in the board-test environment, since it allows the board-level automated test equipment (ATE) to treat the ASP as a simple transceiver. When the BYP\ input is high, the ASP is free to respond to shadow protocols. Otherwise, when BYP\ is low, shadow protocols are ignored. Whether the connected status is achieved by use of shadow protocol or by use of BYP\, this status is indicated by a low level at the connect (CON\) output. Likewise, when the secondary TAP is disconnected from the primary TAP, the CON\ output is high. The SN54LVT8996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT8996 is characterized for operation from -40°C to 85°C. The 'LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit assemblies. Unlike most SCOPETMdevices, the ASP is not a boundary-scannable device, rather, it applies TI's addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test access port (TAP) to extend scan access beyond the board level. These devices are functionally equivalent to the 'ABT8996 ASPs. Additionally, they are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to interface to 5-V masters and/or targets. Conceptually, the ASP is a simple switch that can be used to directly connect a set of multidrop primary TAP signals to a set of secondary TAP signals - for example, to interface backplane TAP signals to a board-level TAP. The ASP provides all signal buffering that might be required at these two interfaces. When primary and secondary TAPs are connected, only a moderate propagation delay is introduced - no storage/retiming elements are inserted. This minimizes the need for reformatting board-level test vectors for in-system use. Most operations of the ASP are synchronous to the primary test clock (PTCK) input. PTCK is always buffered directly onto the secondary test clock (STCK) output. Upon power up of the device, the ASP assumes a condition in which the primary TAP is disconnected from the secondary TAP (unless the bypass signal is used, as below). This reset condition also can be entered by the assertion of the primary test reset (PTRST\) input or by use of shadow protocol. PTRST\ is always buffered directly onto the secondary test reset (STRST\) output, ensuring that the ASP and its associated secondary TAP can be reset simultaneously. When connected, the primary test data input (PTDI) and primary test mode select (PTMS) input are buffered onto the secondary test data output (STDO) and secondary test mode select (STMS) output, respectively, while the secondary test data input (STDI) is buffered onto the primary test data output (PTDO). When disconnected, STDO is at high impedance, while PTDO is at high impedance, except during acknowledgment of a shadow protocol. Upon disconnect of the secondary TAP, STMS holds its last low or high level, allowing the secondary TAP to be held in its last stable state. Upon reset of the ASP, STMS is high, allowing the secondary TAP to be synchronously reset to the Test-Logic-Reset state. In system, primary-to-secondary connection is based on shadow protocols that are received and acknowledged on PTDI and PTDO, respectively. These protocols can occur in any of the stable TAP states other than Shift-DR or Shift-IR (i.e., Test-Logic-Reset, Run-Test/Idle, Pause-DR or Pause-IR). The essential nature of the protocols is to receive/transmit an address via a serial bit-pair signaling scheme. When an address is received serially at PTDI that matches that at the parallel address inputs (A9-A0), the ASP serially retransmits its address at PTDO as an acknowledgment and then assumes the connected (ON) status, as above. If the received address does not match that at the address inputs, the ASP immediately assumes the disconnected (OFF) status without acknowledgment. The ASP also supports three dedicated addresses that can be received globally (that is, to which all ASPs respond) during shadow protocols. Receipt of the dedicated disconnect address (DSA) causes the ASP to disconnect in the same fashion as a nonmatching address. Reservation of this address for global use ensures that at least one address is available to disconnect all receiving ASPs. The DSA is especially useful when the secondary TAPs of multiple ASPs are to be left in different stable states. Receipt of the reset address (RSA) causes the ASP to assume the reset condition, as above. Receipt of the test-synchronization address (TSA) causes the ASP to assume a connect status (MULTICAST) in which PTDO is at high impedance but the connections from PTMS to STMS and PTDI to STDO are maintained to allow simultaneous operation of the secondary TAPs of multiple ASPs. This is useful for multicast TAP-state movement, simultaneous test operation (such as in Run-Test/Idle state), and scanning of common test data into multiple like scan chains. The TSA is valid only when received in the Pause-DR or Pause-IR TAP states. Alternatively, primary-to-secondary connection can be selected by assertion of a low level at the bypass (BYP\) input. This operation is asynchronous to PTCK and is independent of PTRST\ and/or power-up reset. This bypassing feature is especially useful in the board-test environment, since it allows the board-level automated test equipment (ATE) to treat the ASP as a simple transceiver. When the BYP\ input is high, the ASP is free to respond to shadow protocols. Otherwise, when BYP\ is low, shadow protocols are ignored. Whether the connected status is achieved by use of shadow protocol or by use of BYP\, this status is indicated by a low level at the connect (CON\) output. Likewise, when the secondary TAP is disconnected from the primary TAP, the CON\ output is high. The SN54LVT8996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT8996 is characterized for operation from -40°C to 85°C.

These bus buffers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE)\ input is high. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. These bus buffers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the high-impedance state when the associated output-enable (OE)\ input is high. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCCis between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for hot-insertion applications using Ioffand power-up 3-state. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.