SN74LVT543 Series

3.3-V ABT Octal Registered Transceivers With 3-State Outputs

Catalog

3.3-V ABT Octal Registered Transceivers With 3-State Outputs

Part	Package / Case [custom]	Package / Case	Package / Case [custom]	Output Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Bits per Element	Supplier Device Package	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Number of Elements	Mounting Type
Texas Instruments SN74LVT543DWR	7.5 mm	24-SOIC	0.295 in	3-State	2.7 V	3.6 V	8	24-SOIC	64 mA	32 mA	85 °C	-40 °C	1	Surface Mount
Texas Instruments SN74LVT543DW	7.5 mm	24-SOIC	0.295 in	3-State	2.7 V	3.6 V	8	24-SOIC	64 mA	32 mA	85 °C	-40 °C	1	Surface Mount

Catalog

3.3-V ABT Octal Registered Transceivers With 3-State Outputs

Key Features

• State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)Support Unregulated Battery Operation Down to 2.7 VTypical VOLP(Output Ground Bounce)< 0.8 V at VCC= 3.3 V, TA= 25°CESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Bus-Hold Data Inputs Eliminate the Need for External Pullup ResistorsSupport Live InsertionPackage Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (JT) DIPsState-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power DissipationSupport Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)Support Unregulated Battery Operation Down to 2.7 VTypical VOLP(Output Ground Bounce)< 0.8 V at VCC= 3.3 V, TA= 25°CESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17Bus-Hold Data Inputs Eliminate the Need for External Pullup ResistorsSupport Live InsertionPackage Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Ceramic (JT) DIPs

Description

These octal transceivers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The 'LVT543 contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (or) and output-enable(or) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable () input must be low in order to enter data from A or to output data from B. Ifis low andis low, the A-to-B latches are transparent; a subsequent low-to-high transition ofputs the A latches in the storage mode. Withandboth low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the,, andinputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT543 is characterized for operation from -40°C to 85°C. These octal transceivers are designed specifically for low-voltage (3.3-V) VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment. The 'LVT543 contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (or) and output-enable(or) inputs are provided for each register to permit independent control in either direction of data flow. The A-to-B enable () input must be low in order to enter data from A or to output data from B. Ifis low andis low, the A-to-B latches are transparent; a subsequent low-to-high transition ofputs the A latches in the storage mode. Withandboth low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the,, andinputs. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down,should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT543 is characterized for operation from -40°C to 85°C.