| Integrated Circuits (ICs) | 1 | Obsolete | The SN54LS297 and SN74LS297 devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the divide-by-N counter, to build first order phase-locked loops as described in Figure 1.
Both exclusive-OR (XORPD) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility.
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher order phase-locked loops.
The length of the up/down K counter is digitally programmable according to the K counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C, and D are all programmed high, the K counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A through D inputs can maximize the overall performance of the digital phase-locked loop.FIGURE 1-SIMPLIFIED BLOCK DIAGRAM
The 'LS297 can perform the classic first-order phase-locked loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCCand temperature variations, but depends solely on accuracies of the K clock, I/D clock, and loop propagation delays. The I/D clock frequency and the divide-by-N modulos will determine the center frequency of the DPLL. The center frequency is defined by the relationship fc= I/D Clock /2N(Hz).
The SN54LS297 and SN74LS297 devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the divide-by-N counter, to build first order phase-locked loops as described in Figure 1.
Both exclusive-OR (XORPD) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility.
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy for the designer to incorporate ripple cancellation or to cascade to higher order phase-locked loops.
The length of the up/down K counter is digitally programmable according to the K counter function table. With A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B, C, and D are all programmed high, the K counter becomes seventeen stages long, which narrows the bandwidth or capture range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A through D inputs can maximize the overall performance of the digital phase-locked loop.FIGURE 1-SIMPLIFIED BLOCK DIAGRAM
The 'LS297 can perform the classic first-order phase-locked loop function without using analog components. The accuracy of the digital phase-locked loop (DPLL) is not affected by VCCand temperature variations, but depends solely on accuracies of the K clock, I/D clock, and loop propagation delays. The I/D clock frequency and the divide-by-N modulos will determine the center frequency of the DPLL. The center frequency is defined by the relationship fc= I/D Clock /2N(Hz). |
| Shift Registers | 3 | Active | These Schottky TTL eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are enabled or off.
These Schottky TTL eight-bit universal registers feature multiplexed inputs/outputs to achieve full eight-bit data handling in a single 20-pin package. Two function-select inputs and two output-control inputs can be used to choose the modes of operation listed in the function table.
Synchronous parallel loading is accomplished by taking both function-select lines, S0 and S1, high. This places the three-state outputs in a high-impedance state, which permits data that is applied on the input/output lines to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. A direct overriding input is provided to clear the register whether the outputs are enabled or off. |
SN74LS30Single 8-input, 4.75-V to 5.25-V bipolar NAND gate | Logic | 3 | Active | These devices contain a single 8-input NAND gate.
The SN5430, SN54LS30, and SN54S30 are characterized for operation over the full military range of -55°C to 125°C. The SN7430, SN74LS30, and SN74S30 are characterized for operation from 0°C to 70°C.
These devices contain a single 8-input NAND gate.
The SN5430, SN54LS30, and SN54S30 are characterized for operation over the full military range of -55°C to 125°C. The SN7430, SN74LS30, and SN74S30 are characterized for operation from 0°C to 70°C. |
SN74LS316-ch, 4.75-V to 5.25-V bipolar buffers | Specialty Logic | 4 | Active | These 'LS31 delay elements are intended to provide well-defined delays across both temperature and VCCranges. Used in cascade, a limitless range of delay gating is possible.
All inputs are PNP with IILMAX of -0.2 mA. Gates 1, 2, 5, and 6 have standard Low-Power Schottky output sink current capability of 4 and 8 mA IOL. Buffers 3 and 4 are rated at 12 and 24 mA.
The SN54LS31 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS31 is characterized for operation from 0°C to 70°C.
These 'LS31 delay elements are intended to provide well-defined delays across both temperature and VCCranges. Used in cascade, a limitless range of delay gating is possible.
All inputs are PNP with IILMAX of -0.2 mA. Gates 1, 2, 5, and 6 have standard Low-Power Schottky output sink current capability of 4 and 8 mA IOL. Buffers 3 and 4 are rated at 12 and 24 mA.
The SN54LS31 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LS31 is characterized for operation from 0°C to 70°C. |
SN74LS324-ch, 2-input, 4.75-V to 5.25-V, 16-mA drive strength bipolar OR gate with TTL-compatible inputs | Gates and Inverters | 8 | Active | These devices contain four independent 2-input OR gates.
The SN5432, SN54LS32 and SN54S32 are characterized for operation over the full military range of -55°C to 125°C. The SN7432, SN74LS32 and SN74S32 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input OR gates.
The SN5432, SN54LS32 and SN54S32 are characterized for operation over the full military range of -55°C to 125°C. The SN7432, SN74LS32 and SN74S32 are characterized for operation from 0°C to 70°C. |
SN74LS334-ch, 2-input, 4.75-V to 5.25-V bipolar NOR gates with open-collector outputs | Gates and Inverters | 4 | Active | These devices contain four independent 2-input NOR buffer gates with open-collector outputs. Open-collector outputs require resistive pull-up to perform logically but can deliver higher VOHlevels and are commonly used in wired-AND applications.
The SN5433 and SN54LS33 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7433, and SN74LS33 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input NOR buffer gates with open-collector outputs. Open-collector outputs require resistive pull-up to perform logically but can deliver higher VOHlevels and are commonly used in wired-AND applications.
The SN5433 and SN54LS33 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7433, and SN74LS33 are characterized for operation from 0°C to 70°C. |
SN74LS365A6-ch, 4.75-V to 5.25-V bipolar buffers with 3-state outputs | Logic | 1 | Active | These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The designer has choice of selected combinations of inverting and noninverting outputs, symmetrical G\ (active-low control) inputs.
These devices feature high fan-out, improved fan-in, and can be used to drive terminated lines down to 133 ohms.
The SN54365A thru SN54368A and SN54LS365A thru SN54LS368A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74365A thru SN74368A and SN74LS365A thru SN74LS368A are characterized for operation from 0°C to 70°C.
These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The designer has choice of selected combinations of inverting and noninverting outputs, symmetrical G\ (active-low control) inputs.
These devices feature high fan-out, improved fan-in, and can be used to drive terminated lines down to 133 ohms.
The SN54365A thru SN54368A and SN54LS365A thru SN54LS368A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74365A thru SN74368A and SN74LS365A thru SN74LS368A are characterized for operation from 0°C to 70°C. |
SN74LS367A6-ch, 4.75-V to 5.25-V bipolar buffers with 3-state outputs | Logic | 4 | Active | These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The designer has choice of selected combinations of inverting and noninverting outputs, symmetrical G\ (active-low control) inputs.
These devices feature high fan-out, improved fan-in, and can be used to drive terminated lines down to 133 ohms.
The SN54365A thru SN54368A and SN54LS365A thru SN54LS368A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74365A thru SN74368A and SN74LS365A thru SN74LS368A are characterized for operation from 0°C to 70°C.
These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The designer has choice of selected combinations of inverting and noninverting outputs, symmetrical G\ (active-low control) inputs.
These devices feature high fan-out, improved fan-in, and can be used to drive terminated lines down to 133 ohms.
The SN54365A thru SN54368A and SN54LS365A thru SN54LS368A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74365A thru SN74368A and SN74LS365A thru SN74LS368A are characterized for operation from 0°C to 70°C. |
SN74LS368A6-ch, 4.75-V to 5.25-V bipolar inverters with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 3 | Active | These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The designer has choice of selected combinations of inverting and noninverting outputs, symmetrical G\ (active-low control) inputs.
These devices feature high fan-out, improved fan-in, and can be used to drive terminated lines down to 133 ohms.
The SN54365A thru SN54368A and SN54LS365A thru SN54LS368A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74365A thru SN74368A and SN74LS365A thru SN74LS368A are characterized for operation from 0°C to 70°C.
These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus oriented receivers and transmitters. The designer has choice of selected combinations of inverting and noninverting outputs, symmetrical G\ (active-low control) inputs.
These devices feature high fan-out, improved fan-in, and can be used to drive terminated lines down to 133 ohms.
The SN54365A thru SN54368A and SN54LS365A thru SN54LS368A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74365A thru SN74368A and SN74LS365A thru SN74LS368A are characterized for operation from 0°C to 70°C. |
SN74LS374-ch, 2-input, 4.75-V to 5.25-V bipolar NAND gates | Integrated Circuits (ICs) | 2 | Active | These devices contain four independent 2-input NAND buffer gates.
The SN5437, SN54LS37 and SN54S37 are characterized for operation over the full military range of -55°C to 125°C. The SN7437, SN74LS37 and SN74S37 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input NAND buffer gates.
The SN5437, SN54LS37 and SN54S37 are characterized for operation over the full military range of -55°C to 125°C. The SN7437, SN74LS37 and SN74S37 are characterized for operation from 0°C to 70°C. |
