Texas Instruments

The SN74HC10 device contains three independent 3-input NAND gates. It performs the Boolean function Y = (A • B • C)\ or Y = A\ + B\ + C\ in positive logic. The SN74HC10 device contains three independent 3-input NAND gates. It performs the Boolean function Y = (A • B • C)\ or Y = A\ + B\ + C\ in positive logic.

This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic. This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic.

This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic. This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic.

This device contains four independent 2-input NAND gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A ● Bin positive logic. This device contains four independent 2-input NAND gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A ● Bin positive logic.

The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN74HC138 is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The conditions at the binary-select inputs at the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enableGinput can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit. The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enableGinput can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

This device contains six independent inverters with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic. This device contains six independent inverters with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic.

The SNx4HC148 is an 8-input priority encoder. Added input enable (EI) and output enable (EO) signals allow for cascading multiple stages without added external circuitry. The SNx4HC148 is an 8-input priority encoder. Added input enable (EI) and output enable (EO) signals allow for cascading multiple stages without added external circuitry.

8-Line To 1-Line Data Selectors/Multiplexers

The ’HC153 and ’HCT153 are dual 4- to 1-line selector/multiplexers that select one of four sources for each section by the common select inputs, S0 and S1. When the enable inputs (1E\, 2E\) are HIGH, the outputs are in the LOW state. The ’HC153 and ’HCT153 are dual 4- to 1-line selector/multiplexers that select one of four sources for each section by the common select inputs, S0 and S1. When the enable inputs (1E\, 2E\) are HIGH, the outputs are in the LOW state.