| Logic | 5 | Active | The ´BCT640 bus transceiver is designed for asynchronous communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction-control (DIR) input. The output-enable () input can be used to disable the device so that the buses are effectively isolated.
The SN54BCT640 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT640 is characterized for operation from 0°C to 70°C.
The ´BCT640 bus transceiver is designed for asynchronous communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at the direction-control (DIR) input. The output-enable () input can be used to disable the device so that the buses are effectively isolated.
The SN54BCT640 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT640 is characterized for operation from 0°C to 70°C. |
| Buffers, Drivers, Receivers, Transceivers | 3 | Active | These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
Output-enable (OEAB and) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ´BCT652.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and. In this configuration each output reinforces its input. Therefore, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remain at its last state.
The SN54BCT652 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT652 is characterized for operation from 0°C to 70°C.
These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers.
Output-enable (OEAB and) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ´BCT652.
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and. In this configuration each output reinforces its input. Therefore, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remain at its last state.
The SN54BCT652 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT652 is characterized for operation from 0°C to 70°C. |
SN74BCT7568-ch, 4.5-V to 5.5-V inverters with open-collector outputs | Buffers, Drivers, Receivers, Transceivers | 2 | Active | This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74BCT756, SN74BCT757, and SN74BCT760 provide the choice of selected combinations of inverting outputs, symmetrical output-enable (OE\) inputs, and complementary OE and OE\ inputs.
The SN74BCT756 is characterized for operation from 0°C to 70°C.
This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74BCT756, SN74BCT757, and SN74BCT760 provide the choice of selected combinations of inverting outputs, symmetrical output-enable (OE\) inputs, and complementary OE and OE\ inputs.
The SN74BCT756 is characterized for operation from 0°C to 70°C. |
SN74BCT7578-ch, 4.5-V to 5.5-V buffers with open-collector outputs | Logic | 4 | Active | This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device provides complementary output-enable (OE and) inputs and noninverting outputs.
The SN74BCT757 is characterized for operation from 0°C to 70°C.
This octal buffer and line driver is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device provides complementary output-enable (OE and) inputs and noninverting outputs.
The SN74BCT757 is characterized for operation from 0°C to 70°C. |
SN74BCT760-EPEnhanced product 8-ch, -0.5-V to 7-V buffers with open-collector outputs | Logic | 6 | Active | These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The ´BCT760 is organized as two 4-bit buffers/line drivers with separate output-enable () inputs. Whenis low, the device passes data from the A inputs to the Y outputs. Whenis high, the outputs are in the high-impedance state.
The SN54BCT760 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT760 is characterized for operation from 0°C to 70°C.
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The ´BCT760 is organized as two 4-bit buffers/line drivers with separate output-enable () inputs. Whenis low, the device passes data from the A inputs to the Y outputs. Whenis high, the outputs are in the high-impedance state.
The SN54BCT760 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT760 is characterized for operation from 0°C to 70°C. |
SN74BCT8244AIEEE Std 1149.1 (JTAG) Boundary-Scan Test Device With Octal Buffers | Integrated Circuits (ICs) | 4 | Active | The 'BCT8244A scan test devices with octal buffers are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F244 and 'BCT244 octal buffers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETMoctal buffers.
In the test mode, the normal operation of the SCOPETMoctal buffers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations, as described in IEEE Standard 1149.1-1990.
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8244A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8244A is characterized for operation from 0°C to 70°C.
The 'BCT8244A scan test devices with octal buffers are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F244 and 'BCT244 octal buffers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETMoctal buffers.
In the test mode, the normal operation of the SCOPETMoctal buffers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations, as described in IEEE Standard 1149.1-1990.
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8244A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8244A is characterized for operation from 0°C to 70°C. |
SN74BCT8245AIEEE Std 1149.1 (JTAG) Boundary-Scan Test Device With Octal Bus Transceivers | Integrated Circuits (ICs) | 1 | Active | The 'BCT8245A scan test devices with octal bus transceivers are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F245 and 'BCT245 octal bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETMoctal bus transceivers.
In the test mode, the normal operation of the SCOPETMoctal bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8245A is characterized for operation from 0°C to 70°C.
The 'BCT8245A scan test devices with octal bus transceivers are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F245 and 'BCT245 octal bus transceivers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETMoctal bus transceivers.
In the test mode, the normal operation of the SCOPETMoctal bus transceivers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8245A is characterized for operation from 0°C to 70°C. |
SN74BCT8374AScan Test Device With Octal D-Type Edge-Triggered Flip-Flops | Logic | 5 | Active | The 'BCT8374A scan test devices with octal edge-triggered D-type flip-flops are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F374 and 'BCT374 octal D-type flip-flops. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETMoctal flip-flops.
In the test mode, the normal operation of the SCOPETMoctal flip-flops is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8374A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8374A is characterized for operation from 0°C to 70°C.
The 'BCT8374A scan test devices with octal edge-triggered D-type flip-flops are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are functionally equivalent to the 'F374 and 'BCT374 octal D-type flip-flops. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device terminals or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETMoctal flip-flops.
In the test mode, the normal operation of the SCOPETMoctal flip-flops is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry can perform boundary-scan test operations as described in IEEE Standard 1149.1-1990.
Four dedicated test terminals control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
The SN54BCT8374A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT8374A is characterized for operation from 0°C to 70°C. |
| Unclassified | 1 | Obsolete | |
SN74CB3Q162103.3-V, 1:1 (SPST), 20-channel FET bus switch with 2 control inputs | Logic | 2 | Active | The SN74CB3Q16210 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16210 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.
The SN74CB3Q16210 is organized as two 10-bit bus switches with separate output-enable (1OE\, 2OE\) inputs. It can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE\ is low, the associated 10-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CB3Q16210 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16210 provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.
The SN74CB3Q16210 is organized as two 10-bit bus switches with separate output-enable (1OE\, 2OE\) inputs. It can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE\ is low, the associated 10-bit bus switch is ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
