| Buffers, Drivers, Receivers, Transceivers | 2 | Active | The ´BCT25245 is a 25-octal bus transceiver designed for asynchronous communication between data buses. It improves both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers.
The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction-control (DIR) input. The output-enable () input can disable the device so that both buses are effectively isolated.
These transceivers are capable of sinking 188-mA IOL, which facilitates switching 25-transmission lines on the incident wave. The distributed VCCand GND pins minimize switching noise for more reliable system operation.
The SN54BCT25245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT25245 is characterized for operation from 0°C to 70°C.
The ´BCT25245 is a 25-octal bus transceiver designed for asynchronous communication between data buses. It improves both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented transceivers.
The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon the logic level at the direction-control (DIR) input. The output-enable () input can disable the device so that both buses are effectively isolated.
These transceivers are capable of sinking 188-mA IOL, which facilitates switching 25-transmission lines on the incident wave. The distributed VCCand GND pins minimize switching noise for more reliable system operation.
The SN54BCT25245 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT25245 is characterized for operation from 0°C to 70°C. |
SN74BCT2827C10-ch, 4.5-V to 5.5-V buffers with 3-state outputs | Integrated Circuits (ICs) | 3 | Active | These 10-bit buffers and bus drivers are specifically designed to drive the capacitive input characteristics of MOS DRAMs. They provide high-performance bus interface for wide data paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with active-low inputs so if either output-enable (or) input is high, all ten outputs are in the high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down.
The SN54BCT2827C is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT2827C is characterized for operation from 0°C to 70°C.
These 10-bit buffers and bus drivers are specifically designed to drive the capacitive input characteristics of MOS DRAMs. They provide high-performance bus interface for wide data paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with active-low inputs so if either output-enable (or) input is high, all ten outputs are in the high-impedance state. The outputs are also in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down.
The SN54BCT2827C is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT2827C is characterized for operation from 0°C to 70°C. |
| Specialty Logic | 2 | Active | The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error () output will indicate whether or not an error in the B data has occurred. The output-enable (,) inputs can be used to disable the device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error () flag.can be either passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error () output will indicate whether or not an error in the B data has occurred. The output-enable (,) inputs can be used to disable the device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error () flag.can be either passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C. |
| Buffers, Drivers, Receivers, Transceivers | 2 | Active | These 9-bit transceivers are designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing.
These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the output-enable (and) inputs.
The outputs are in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down.
The SN54BCT29863B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT29863B is characterized for operation from 0°C to 70°C.
These 9-bit transceivers are designed for asynchronous communication between data buses. The control-function implementation allows for maximum flexibility in timing.
These devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the output-enable (and) inputs.
The outputs are in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down.
The SN54BCT29863B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT29863B is characterized for operation from 0°C to 70°C. |
| Flip Flops | 6 | Active | The SNx4BCT374 devices contain eight channels of D-type flip-flops with a shared clock (CLK) and output enable (OE) pin.
The SNx4BCT374 devices contain eight channels of D-type flip-flops with a shared clock (CLK) and output enable (OE) pin. |
SN74BCT540A8-ch, 4.5-V to 5.5-V inverters with 3-state outputs | Integrated Circuits (ICs) | 3 | Active | The SN54BCT540 and SN74BCT540A octal buffers and line drivers are ideal for driving bus lines or buffer memory-address registers. The devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all corresponding outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54BCT540 and SN74BCT540A octal buffers and line drivers are ideal for driving bus lines or buffer memory-address registers. The devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1\ or OE2\) input is high, all corresponding outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
SN74BCT541A10-ch, 4.5-V to 5.5-V buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 3 | Active | The SN54BCT541 and SN74BCT541A octal buffers and line drivers are ideal for driving bus lines or buffering memory-address registers. The devices feature inputs and outputs on opposite sides of the package to facilitate printed-circuit-board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54BCT541 and SN74BCT541A octal buffers and line drivers are ideal for driving bus lines or buffering memory-address registers. The devices feature inputs and outputs on opposite sides of the package to facilitate printed-circuit-board layout.
The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1\ or OE2\) input is high, all eight outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Buffers, Drivers, Receivers, Transceivers | 3 | Active | The 'BCT543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB\) input must be low in order to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA\, LEBA\, and OEBA\ inputs.
The SN54BCT543 is characterized for operation over the full military temperature range of \x9655°C to 125°C. The SN74BCT543 is characterized for operation from 0°C to 70°C.
The 'BCT543 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (LEAB\ or LEBA\) and output-enable (OEAB\ or OEBA\) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB\) input must be low in order to enter data from A or to output data from B. If CEAB\ is low and LEAB\ is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB\ puts the A latches in the storage mode. With CEAB\ and OEAB\ both low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the CEBA\, LEBA\, and OEBA\ inputs.
The SN54BCT543 is characterized for operation over the full military temperature range of \x9655°C to 125°C. The SN74BCT543 is characterized for operation from 0°C to 70°C. |
| Integrated Circuits (ICs) | 2 | Active | These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
(OE)\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight latches of the ’BCT573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When the latch enable is taken low, the Q outputs are latched at the logic levels that were set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
(OE)\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. |
| Flip Flops | 2 | Active | These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the ’BCT574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
(OE)\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops of the ’BCT574 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
To ensure the high-impedance state during power up or power down, (OE)\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
(OE)\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. |
