Catalog
8-Bit To 9-Bit Parity Transceivers
Key Features
• BiCMOS Process With TTL Inputs and OutputsState-of-the-Art BiCMOS Design Significantly Reduces Standby CurrentFlow-Through Pinout (All Inputs on Opposite Side From Outputs)Functionally Equivalent to AMD Am29854High-Speed Bus Transceiver With Parity Generator/CheckerParity-Error Flag With Open-Collector OutputLatch for Storage of the Parity-Error FlagPackage Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)BiCMOS Process With TTL Inputs and OutputsState-of-the-Art BiCMOS Design Significantly Reduces Standby CurrentFlow-Through Pinout (All Inputs on Opposite Side From Outputs)Functionally Equivalent to AMD Am29854High-Speed Bus Transceiver With Parity Generator/CheckerParity-Error Flag With Open-Collector OutputLatch for Storage of the Parity-Error FlagPackage Options Include Plastic Small-Outline (DW) Packages and Standard Plastic 300-mil DIPs (NT)
Description
AI
The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error () output will indicate whether or not an error in the B data has occurred. The output-enable (,) inputs can be used to disable the device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error () flag.can be either passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
The SN74BCT29854 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted from the B to A bus with its corresponding parity bit, the parity-error () output will indicate whether or not an error in the B data has occurred. The output-enable (,) inputs can be used to disable the device so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with an open-collector parity-error () flag.can be either passed, sampled, stored, or cleared from the latch using the latch-enable () and clear () control inputs. When bothandare low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition which gives the designer more system diagnostic capability. The SN74BCT29854 provides inverting logic.
The SN74BCT29854 is characterized for operation from 0°C to 70°C.
