T
Texas Instruments
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Part | Spec A | Spec B | Spec C | Spec D | Description |
|---|---|---|---|---|---|
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Part | Spec A | Spec B | Spec C | Spec D | Description |
|---|---|---|---|---|---|
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
SN74AUP2G79Low-Power Dual Positive-Edge-Triggered D-Type Flip-Flop | Integrated Circuits (ICs) | 4 | Active | The AUP family is TI’s premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see ). This product also maintains excellent signal integrity.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The AUP family is TI’s premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see ). This product also maintains excellent signal integrity.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74AUP2G80Low-Power Dual Positive-Edge-Triggered D-Type Flip-Flop | Integrated Circuits (ICs) | 2 | Active | The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74AUP3G043-ch, 0.8-V to 3.6-V low power inverters | Integrated Circuits (ICs) | 3 | Active | The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
The SN74AUP3G04 performs the Boolean function Y = A in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
The SN74AUP3G04 performs the Boolean function Y = A in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74AUP3G063-ch, 0.8-V to 3.6-V low power inverters with open-drain outputs | Integrated Circuits (ICs) | 2 | Active | The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
The output of SN74AUP3G06 is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
The output of SN74AUP3G06 is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74AUP3G073-ch, 0.8-V to 3.6-V low power buffers with open-drain outputs | Integrated Circuits (ICs) | 3 | Active | The AUP family is TI’s premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see ). This product also maintains excellent signal integrity.
The output of SN74AUP3G07 is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The AUP family is TI’s premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see ). This product also maintains excellent signal integrity.
The output of SN74AUP3G07 is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74AUP3G143-ch, 0.8-V to 3.6-V low power inverters with Schmitt-Trigger inputs | Integrated Circuits (ICs) | 2 | Active | The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity.
The SN74AUP3G14 contains three inverters and performs the Boolean function Y =A. The device functions as three independent inverters but, because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity.
The SN74AUP3G14 contains three inverters and performs the Boolean function Y =A. The device functions as three independent inverters but, because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74AUP3G173-ch, 0.8-V to 3.6-V low power buffers with Schmitt-Trigger inputs | Buffers, Drivers, Receivers, Transceivers | 4 | Active | The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity.
The SN74LVC3G17 contains three buffers and performs the Boolean function Y = A. The device functions as three independent buffers but, because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life. This product also maintains excellent signal integrity.
The SN74LVC3G17 contains three buffers and performs the Boolean function Y = A. The device functions as three independent buffers but, because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74AUP3G343-ch, 0.8-V to 3.6-V low power buffers | Integrated Circuits (ICs) | 5 | Active | The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
The SN74AUP3G34 performs the Boolean function Y = A in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCCrange of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
The SN74AUP3G34 performs the Boolean function Y = A in positive logic.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74AVC1624416-ch, 1.4-V to 3.6-V buffers with 3-state outputs | Logic | 4 | Active | A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,AVC Logic Family Technology and Applications, literature number SCEA006, andDynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.
This 16-bit buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation.
The SN74AVC16244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE\) inputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,AVC Logic Family Technology and Applications, literature number SCEA006, andDynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.
This 16-bit buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation.
The SN74AVC16244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE\) inputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
SN74AVC1624516-Bit Bus Transceiver With 3-State Outputs | Buffers, Drivers, Receivers, Transceivers | 2 | Active | A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,AVC Logic Family Technology and Applications, literature number SCEA006, andDynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.
This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation.
The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can be used to disable the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74AVC16245 is characterized for operation from -40°C to 85°C.
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,AVC Logic Family Technology and Applications, literature number SCEA006, andDynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009.
This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation.
The SN74AVC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE\) input can be used to disable the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74AVC16245 is characterized for operation from -40°C to 85°C. |
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