SN74AVC16244 Series

16-ch, 1.4-V to 3.6-V buffers with 3-state outputs

Catalog

16-ch, 1.4-V to 3.6-V buffers with 3-state outputs

Part	Logic Type	Number of Elements	Output Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Number of Bits per Element	Package / Case	Package / Case	Supplier Device Package	Package / Case [custom]
Texas Instruments SN74AVC16244DGVR	Buffer Non-Inverting	4	3-State	1.4 V	3.6 V	85 °C	-40 °C	12 mA	12 mA	Surface Mount	4	0.173 in 4.4 mm	48-TFSOP
Texas Instruments SN74AVC16244DGGR	Buffer Non-Inverting	4	3-State	1.4 V	3.6 V	85 °C	-40 °C	12 mA	12 mA	Surface Mount	4	0.24 in	48-TFSOP	48-TSSOP	6.1 mm
Texas Instruments SN74AVC16244ZQLR	Buffer Non-Inverting	4	3-State	1.4 V	3.6 V	85 °C	-40 °C	12 mA	12 mA	Surface Mount	4		56-VFBGA	56-BGA Microstar Junior (7x4.5)
Texas Instruments SN74AVC16244GQLR	Buffer Non-Inverting	4	3-State	1.4 V	3.6 V	85 °C	-40 °C	12 mA	12 mA	Surface Mount	4		56-VFBGA	56-BGA Microstar Junior (7x4.5)

Catalog

16-ch, 1.4-V to 3.6-V buffers with 3-state outputs

Key Features

• Member of the Texas Instruments Widebus™ FamilyDOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed DegradationLess Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCCDynamic Drive Capability Is Equivalent to Standard Outputs With IOHand IOLof ±24 mA at 2.5-V VCCOvervoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data CommunicationsIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)DOC and Widebus are trademarks of Texas Instruments.Member of the Texas Instruments Widebus™ FamilyDOC™ (Dynamic Output Control) Circuit Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed DegradationLess Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V VCCDynamic Drive Capability Is Equivalent to Standard Outputs With IOHand IOLof ±24 mA at 2.5-V VCCOvervoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data CommunicationsIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)DOC and Widebus are trademarks of Texas Instruments.

Description

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,AVC Logic Family Technology and Applications, literature number SCEA006, andDynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009. This 16-bit buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation. The SN74AVC16244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE\) inputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOLvs IOLand VOHvs IOHcurves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,AVC Logic Family Technology and Applications, literature number SCEA006, andDynamic Output Control (DOCTM) Circuitry Technology and Applications, literature number SCEA009. This 16-bit buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCCoperation. The SN74AVC16244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE\) inputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.