SN74AS2869-Bit Parity Generators/Checkers With Bus-Driver Parity I/O Ports | Parity Generators and Checkers | 3 | Active | The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-drivingparity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading.
The transmit () control input is implemented specifically to accommodate cascading. Whenis low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. Whenis high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches.
The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C.
The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-drivingparity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading.
The transmit () control input is implemented specifically to accommodate cascading. Whenis low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. Whenis high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level.
The I/O control circuitry was designed so that the I/O port remains in the high-impedance state during power up or power down to prevent bus glitches.
The SN54AS286 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS286 is characterized for operation from 0°C to 70°C. |
SN74AS298AQuadruple 2-Input Multiplexers With Storage | Logic | 4 | Active | The SN74AS298A is a quadruple 2-input multiplexer with storage that provides essentially the equivalent functional capabilities of two separate MSI functions (SN74AS157 and ´AS175A) in a 16-pin package.
When the word-select (WS) input is low, word 1 (A1, B1, C1, D1) is applied to the flip-flops. A high input to WS causes the selection of word 2 (A2, B2, C2, D2). The selected word is clocked to the output terminals on the negative-going edge of the clock pulse.
The SN74AS298A is characterized for operation from 0°C to 70°C.
a1, a2, etc. = the level of steady-state input at A1, A2, etc.QA0, QB0, etc. = the level of QA, QB, etc. entered on the most recent transition of CLK
The SN74AS298A is a quadruple 2-input multiplexer with storage that provides essentially the equivalent functional capabilities of two separate MSI functions (SN74AS157 and ´AS175A) in a 16-pin package.
When the word-select (WS) input is low, word 1 (A1, B1, C1, D1) is applied to the flip-flops. A high input to WS causes the selection of word 2 (A2, B2, C2, D2). The selected word is clocked to the output terminals on the negative-going edge of the clock pulse.
The SN74AS298A is characterized for operation from 0°C to 70°C.
a1, a2, etc. = the level of steady-state input at A1, A2, etc.QA0, QB0, etc. = the level of QA, QB, etc. entered on the most recent transition of CLK |
SN74AS30Single 8-input, 4.5-V to 5.5-V bipolar NAND gate | Logic | 3 | Active | These devices contain an 8-input positive-NAND gate and perform the following Boolean functions in positive logic:
Y =A • B •C • D • E • F • G • H
or
Y =A+B+C+D+E+F+G
These devices contain an 8-input positive-NAND gate and perform the following Boolean functions in positive logic:
Y =A • B •C • D • E • F • G • H
or
Y =A+B+C+D+E+F+G |
SN74AS324-ch, 2-input, 4.5-V to 5.5-V ultra-high-speed (4 ns) bipolar OR gate | Logic | 4 | Active | These devices contain four independent 2-input positive-OR gates. They perform the Boolean functionsor Y = A + B in positive logic.
The SN54ALS32 and SN54AS32 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS32 and SN74AS32 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input positive-OR gates. They perform the Boolean functionsor Y = A + B in positive logic.
The SN54ALS32 and SN54AS32 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS32 and SN74AS32 are characterized for operation from 0°C to 70°C. |
SN74AS373Octal D-Type Transparent Latches with 3-state Outputs | Logic | 4 | Active | These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off.
These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. |
SN74AS374Octal D-Type Edge Triggered Flip-Flops with 3-State Outputs | Integrated Circuits (ICs) | 3 | Active | These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C.
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE\) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS374A and SN54AS374 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS374A and SN74AS374 are characterized for operation from 0°C to 70°C. |
SN74AS573AOctal D-Type Transparent Latches With 3-State Outputs | Latches | 3 | Active | These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, outputs (Q) respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.
A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
does not affect internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C.
These octal D-type transparent latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, outputs (Q) respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.
A buffered output-enable () input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components.
does not affect internal operation of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS573C and SN54AS573A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS573C and SN74AS573A are characterized for operation from 0°C to 70°C. |
SN74AS574Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs | Logic | 2 | Active | These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN74ALS575A, SN54AS575, and SN74AS575 may be synchronously cleared by taking the clear () input low.
The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS574B, SN54AS574, and SN54AS575 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS574B, SN74ALS575A, SN74AS574, and SN74AS575 are characterized for operation from 0°C to 70°C.
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN74ALS575A, SN54AS575, and SN74AS575 may be synchronously cleared by taking the clear () input low.
The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54ALS574B, SN54AS574, and SN54AS575 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS574B, SN74ALS575A, SN74AS574, and SN74AS575 are characterized for operation from 0°C to 70°C. |
SN74AS576Octal D-Type Edge-Triggered Flip-Flops With 3-State Outputs | Integrated Circuits (ICs) | 2 | Active | These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These flip-flops enter data on the low-to-high transition of the clock (CLK) input.
The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are disabled.
The SN54ALS576B and SN54AS576 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS576B, SN74ALS577A, and SN74AS576 are characterized for operation from 0°C to 70°C.
These octal D-type edge-triggered flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
These flip-flops enter data on the low-to-high transition of the clock (CLK) input.
The output-enable () input does not affect internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are disabled.
The SN54ALS576B and SN54AS576 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS576B, SN74ALS577A, and SN74AS576 are characterized for operation from 0°C to 70°C. |
SN74AS641Octal Bus Transceivers With Open-Collector Outputs | Buffers, Drivers, Receivers, Transceivers | 4 | Active | These octal bus transceivers are designed for asynchronous two-way communication between
data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enableinput disables the device so that the buses are effectively isolated.
The -1 versions of the SN74ALS641A and SN74ALS642A are identical to the standard versions, except that the recommended maximum IOLis increased to 48 mA in the -1 versions.
The SN74ALS641A, SN74ALS642A, and SN74AS641 are characterized for operation from 0°C to 70°C.
These octal bus transceivers are designed for asynchronous two-way communication between
data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enableinput disables the device so that the buses are effectively isolated.
The -1 versions of the SN74ALS641A and SN74ALS642A are identical to the standard versions, except that the recommended maximum IOLis increased to 48 mA in the -1 versions.
The SN74ALS641A, SN74ALS642A, and SN74AS641 are characterized for operation from 0°C to 70°C. |
