SN74AS645Octal Bus Transceivers With 3-State Outputs | Buffers, Drivers, Receivers, Transceivers | 4 | Active | These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the level at the direction-control (DIR) input. The output-enableinput can be used to disable the device so that the buses are effectively isolated.
The -1 version of the SN74ALS645A is identical to the standard version, except that the recommended maximum IOLis increased to 48 mA. There is no -1 version of the SN54ALS645A.
The SN54ALS645A and SN54AS645 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS645A and SN74AS645 are characterized for operation from 0°C to 70°C.
These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the level at the direction-control (DIR) input. The output-enableinput can be used to disable the device so that the buses are effectively isolated.
The -1 version of the SN74ALS645A is identical to the standard version, except that the recommended maximum IOLis increased to 48 mA. There is no -1 version of the SN54ALS645A.
The SN54ALS645A and SN54AS645 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS645A and SN74AS645 are characterized for operation from 0°C to 70°C. |
SN74AS652Octal Bus Transceivers/Registers With 3-State Outputs | Buffers, Drivers, Receivers, Transceivers | 4 | Active | These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select real-time or stored data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the recommended maximum IOLfor the -1 versions is increased to 48 mA. There are no -1 versions of the SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654.
These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select real-time or stored data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.
The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the recommended maximum IOLfor the -1 versions is increased to 48 mA. There are no -1 versions of the SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654. |
SN74AS74ADual Positive-Edge-Triggered D-Type Flip-Flops With Preset And Clear | Flip Flops | 4 | Active | These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C.
These devices contain two independent positive-edge-triggered D-type flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs regardless of the levels of the other inputs. Whenandare inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of CLK. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
The SN54ALS74A and SN54AS74A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS74A and SN74AS74A are characterized for operation from 0°C to 70°C. |
SN74AS7568-ch, 4.5-V to 5.5-V bipolar inverters with open-collector outputs | Integrated Circuits (ICs) | 3 | Active | These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters by eliminating the need for 3-state overlap protection. The designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. These devices feature high fan-out and improved fan-in.
The SN54AS756 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS756 and SN74AS757 are characterized for operation from 0°C to 70°C.
These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters by eliminating the need for 3-state overlap protection. The designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. These devices feature high fan-out and improved fan-in.
The SN54AS756 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS756 and SN74AS757 are characterized for operation from 0°C to 70°C. |
SN74AS7578-ch, 4.5-V to 5.5-V bipolar buffers with open-collector outputs | Buffers, Drivers, Receivers, Transceivers | 4 | Active | These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters by eliminating the need for 3-state overlap protection. The designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. These devices feature high fan-out and improved fan-in.
The SN54AS756 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS756 and SN74AS757 are characterized for operation from 0°C to 70°C.
These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters by eliminating the need for 3-state overlap protection. The designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. These devices feature high fan-out and improved fan-in.
The SN54AS756 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS756 and SN74AS757 are characterized for operation from 0°C to 70°C. |
SN74AS7608-ch, 4.5-V to 5.5-V bipolar buffers with open-collector outputs | Integrated Circuits (ICs) | 3 | Active | These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters by eliminating the need for 3-state overlap protection. With the ´AS756 and SN74AS757, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs.
The SN54AS760 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS760 and SN74AS760 are characterized for operation from 0°C to 70°C.
These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters by eliminating the need for 3-state overlap protection. With the ´AS756 and SN74AS757, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs.
The SN54AS760 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS760 and SN74AS760 are characterized for operation from 0°C to 70°C. |
SN74AS804BSingle 8-input, 4.5-V to 5.5-V bipolar NAND gate | Gates and Inverters | 4 | Active | These devices contain six independent 2-input NAND drivers. They perform the Boolean functionsor Y = A\ + B\ in positive logic.
The SN54ALS804A and SN54AS804B are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS804A and SN74AS804B are characterized for operation from 0°C to 70°C.
These devices contain six independent 2-input NAND drivers. They perform the Boolean functionsor Y = A\ + B\ in positive logic.
The SN54ALS804A and SN54AS804B are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS804A and SN74AS804B are characterized for operation from 0°C to 70°C. |
SN74AS808B6-ch, 2-input, 4.5-V to 5.5-V ultra-high-speed (4 ns) bipolar AND gate | Integrated Circuits (ICs) | 5 | Active | These devices contain six independent 2-input AND drivers. They perform the Boolean functions Y = A \x95 B orin positive logic.
The SN54AS808B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS808B is characterized for operation from 0°C to 70°C.
These devices contain six independent 2-input AND drivers. They perform the Boolean functions Y = A \x95 B orin positive logic.
The SN54AS808B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS808B is characterized for operation from 0°C to 70°C. |
SN74AS832B6-ch, 2-input, 4.5-V to 5.5-V ultra-high-speed (4 ns) bipolar OR gate | Logic | 3 | Active | These devices contain six independent 2-input OR drivers. They perform the Boolean functions Y = A + B orin positive logic.
The SN54ALS832A and SN54AS832B are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS832A and SN74AS832B are characterized for operation from 0°C to 70°C.
These devices contain six independent 2-input OR drivers. They perform the Boolean functions Y = A + B orin positive logic.
The SN54ALS832A and SN54AS832B are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS832A and SN74AS832B are characterized for operation from 0°C to 70°C. |
| Counters, Dividers | 2 | Obsolete | These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (,) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters. Because loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Two count-enable (and) inputs and a ripple-carry () output are instrumental in accomplishing this function. Bothandmust be low to count. The direction of the count is determined by the levels of the select (S0, S1) inputs as shown in the function table.is fed forward to enable.thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages. Transitions atandare allowed regardless of the level of CLK. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the SN74ALS867A and ´AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q outputs until clocking occurs. For the ´AS867 and ´AS869, any time ENP\ and/or ENT\ is taken high,either goes or remains high. For the SN74ALS867A and SN74ALS869, any timeis taken high,either goes or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for operation from 0°C to 70°C.
These synchronous, presettable, 8-bit up/down counters feature internal-carry look-ahead circuitry for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when so instructed by the count-enable (,) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the eight flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; they may be preset to any number between 0 and 255. The load-input circuitry allows parallel loading of the cascaded counters. Because loading is synchronous, selecting the load mode disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Two count-enable (and) inputs and a ripple-carry () output are instrumental in accomplishing this function. Bothandmust be low to count. The direction of the count is determined by the levels of the select (S0, S1) inputs as shown in the function table.is fed forward to enable.thus enabled produces a low-level pulse while the count is zero (all outputs low) counting down or 255 counting up (all outputs high). This low-level overflow-carry pulse can be used to enable successive cascaded stages. Transitions atandare allowed regardless of the level of CLK. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design.
These counters feature a fully independent clock circuit. With the exception of the asynchronous clear on the SN74ALS867A and ´AS867, changes at S0 and S1 that modify the operating mode have no effect on the Q outputs until clocking occurs. For the ´AS867 and ´AS869, any time ENP\ and/or ENT\ is taken high,either goes or remains high. For the SN74ALS867A and SN74ALS869, any timeis taken high,either goes or remains high. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
The SN54AS867 and SN54AS869 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS867A, SN74ALS869, SN74AS867, and SN74AS869 are characterized for operation from 0°C to 70°C. |
