74AHCT1G125Single 4.5-V to 5.5-V buffer with TTL-compatible CMOS inputs and 3-state outputs | Integrated Circuits (ICs) | 12 | Active | The SN74AHCT1G125 device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable ( OE) input is high. When OE is low, data is passed from the A input to the Y output.
The SN74AHCT1G125 device is a single bus buffer gate/line driver with 3-state output. The output is disabled when the output-enable ( OE) input is high. When OE is low, data is passed from the A input to the Y output. |
| Logic | 9 | Active | |
| Integrated Circuits (ICs) | 11 | Active | |
74AHCT1G32Automotive, 1-channel, 2-input 4.5V to 5.5V high-speed (7.1ns) OR gate with TTL-compatible inputs | Integrated Circuits (ICs) | 12 | Active | The SN74AHCT1G32-Q1 device is a single 2-input positive-OR gate. The device performs the Boolean function Y = A + B in positive logic.
The SN74AHCT1G32-Q1 device is a single 2-input positive-OR gate. The device performs the Boolean function Y = A + B in positive logic. |
74AHCT240Automotive 8-ch, 4.5-V to 5.5-V inverters with TTL-compatible CMOS inputs | Integrated Circuits (ICs) | 11 | Active | This octal buffer/driver is designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SN74AHCT240 device is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A inputs to the Y outputs. WhenOEis high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This octal buffer/driver is designed specifically to improve the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SN74AHCT240 device is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A inputs to the Y outputs. WhenOEis high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
74AHCT244Automotive 8-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs | Integrated Circuits (ICs) | 20 | Active | These octal buffers/drivers are designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
These octal buffers/drivers are designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. |
| Buffers, Drivers, Receivers, Transceivers | 1 | Unknown | |
| Logic | 8 | Active | These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input.
These devices are positive-edge-triggered D-type flip-flops with a direct clear ( CLR) input. |
74AHCT32Enhanced product, 4-ch 2-input 4.5-V to 5.5-V high-speed (7.1 ns) OR gate with TTL-compatible inputs | Gates and Inverters | 21 | Active | The SNx4AHCT32 devices are quadruple 2-input positive-OR gates. These devices perform the Boolean function Y = A × B or Y = A + B in positive logic.
The SNx4AHCT32 devices are quadruple 2-input positive-OR gates. These devices perform the Boolean function Y = A × B or Y = A + B in positive logic. |
74AHCT3676-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs | Buffers, Drivers, Receivers, Transceivers | 10 | Active | The SN74AHCT367 device is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SN74AHCT367 device is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. |
