SN74ALVCH1624416-ch, 1.65-V to 3.6-V buffers with bus-hold and 3-state outputs | Integrated Circuits (ICs) | 8 | Active | This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. |
| Logic | 8 | Active | This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic high or low level applied to prevent excess ICCand ICCZ.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16245 device is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports is always active and must have a logic high or low level applied to prevent excess ICCand ICCZ.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. |
| Integrated Circuits (ICs) | 2 | Active | This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16245-EP is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16245-EP is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. |
SN74ALVCH1626012-Bit To 24-Bit Multiplexed D-Type Latch With 3-State Outputs | Integrated Circuits (ICs) | 4 | Active | This 12-bit to 24-bit multiplexed D-type latch is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B\, OE2B\, and OEA\) inputs control the bus transceiver functions. The OE1B\ and OE2B\ control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16260 is characterized for operation from –40°C to 85°C.
This 12-bit to 24-bit multiplexed D-type latch is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory-interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B\, OE2B\, and OEA\) inputs control the bus transceiver functions. The OE1B\ and OE2B\ control signals also allow bank control in the A-to-B direction.
Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16260 is characterized for operation from –40°C to 85°C. |
SN74ALVCH1626912-bit to 24-bit registered bus exchanger with 3-state outputs | Universal Bus Functions | 3 | Active | This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high-speed microprocessors.
Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKENA)\ inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage register is provided. The select (SEL)\ line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, extending the period during which the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA\, OEB1\, OEB2)\.
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined before the arrival of the first clock pulse.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16269 is used in applications in which two separate ports must be multiplexed onto, or demultiplexed from, a single port. The device is particularly suitable as an interface between synchronous DRAMs and high-speed microprocessors.
Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the appropriate clock-enable (CLKENA)\ inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage register is provided. The select (SEL)\ line selects 1B or 2B data for the A outputs. The register on the A output permits the fastest possible data transfer, extending the period during which the data is valid on the bus. The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by the active-low output enables (OEA\, OEB1\, OEB2)\.
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined before the arrival of the first clock pulse.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. |
SN74ALVCH1627012-bit to 24-bit registered bus exchanger with 3-state outputs | Integrated Circuits (ICs) | 2 | Active | This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus.
The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN\ inputs are low. The select (SEL)\ line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA\ inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA\, OEB\). The control terminals are registered to synchronize the bus-direction changes with CLK.
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16270 is characterized for operation from –40°C to 85°C.
This 12-bit to 24-bit registered bus exchanger is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus.
The device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock (CLK) input when the appropriate CLKEN\ inputs are low. The select (SEL)\ line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA\ inputs allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA\, OEB\). The control terminals are registered to synchronize the bus-direction changes with CLK.
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon as possible, and OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Due to OE\ being routed through a register, the active state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16270 is characterized for operation from –40°C to 85°C. |
SN74ALVCH1627112-bit to 24-bit multiplexed bus exchanger with 3-state outputs | Universal Bus Functions | 1 | Active | This 12-bit to 24-bit bus exchanger is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16271 is intended for applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. This device is particularly suitable as an interface between conventional DRAMs and high-speed microprocessors.
A data is stored in the internal A-to-B registers on the low-to-high transition of the clock (CLK) input, provided that the clock-enable (CLKENA\) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port.
Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput. These latches transfer data when the latch-enable (LE\) inputs are low. The select (SEL\) line selects 1B or 2B data for the A outputs. Data flow is controlled by the active-low output enables (OEA\, OEB\).
To ensure the high-impedance state during power up or power down, the output enables should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 12-bit to 24-bit bus exchanger is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16271 is intended for applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. This device is particularly suitable as an interface between conventional DRAMs and high-speed microprocessors.
A data is stored in the internal A-to-B registers on the low-to-high transition of the clock (CLK) input, provided that the clock-enable (CLKENA\) inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a 24-bit word on the B port.
Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput. These latches transfer data when the latch-enable (LE\) inputs are low. The select (SEL\) line selects 1B or 2B data for the A outputs. Data flow is controlled by the active-low output enables (OEA\, OEB\).
To ensure the high-impedance state during power up or power down, the output enables should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. |
| Flip Flops | 3 | Active | This 20-bit flip-flop is designed for low-voltage 1.65-V to 3.6-V VCCoperation.
The 20 flip-flops of the SN74ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored.
A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-resistors to reduce overshoot and undershoot.
The SN74ALVCH162721 is characterized for operation from –40°C to 85°C.
This 20-bit flip-flop is designed for low-voltage 1.65-V to 3.6-V VCCoperation.
The 20 flip-flops of the SN74ALVCH162721 are edge-triggered D-type flip-flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs if the clock-enable (CLKEN)\ input is low. If CLKEN\ is high, no data is stored.
A buffered output-enable (OE)\ input places the 20 outputs in either a normal logic state (high or low level) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE\ does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-resistors to reduce overshoot and undershoot.
The SN74ALVCH162721 is characterized for operation from –40°C to 85°C. |
SN74ALVCH16282720-ch, 1.65-V to 3.6-V buffers with bus-hold and 3-state outputs | Logic | 4 | Active | This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH162827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
This 20-bit noninverting buffer/driver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH162827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit buffer section, the two output-enable (1OE1\ and 1OE2\ or 2OE1\ and 2OE2\) inputs must both be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. |
| Integrated Circuits (ICs) | 3 | Active | This 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The output port includes equivalent 26-series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162836 is characterized for operation from –40°C to 85°C.
This 20-bit universal bus driver is designed for 1.65-V to 3.6-V VCCoperation.
Data flow from A to Y is controlled by the output-enable (OE\) input. The device operates in the transparent mode when the latch-enable (LE\) input is low. When LE\ is high, the A data is latched if the clock (CLK) input is held at a high or low logic level. If LE\ is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE\ is high, the outputs are in the high-impedance state.
The output port includes equivalent 26-series resistors to reduce overshoot and undershoot.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162836 is characterized for operation from –40°C to 85°C. |
