Texas Instruments

These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits. These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.

The 'ALS191A are synchronous 4-bit reversible up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the count enable () input is low. A high atinhibits counting. The direction of the count is determined by the level of the down/up (D/U\) input. When D/U\ is low, the counter counts up, and when D/U\ is high, the counter counts down. These counters feature a fully independent clock circuit. Changes at the control inputs (and D/U\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the conditions meeting the stable setup and hold times. These counters are fully programmable. Each output can be preset to either level by placing a low on theinput and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. CLK, D/U\, andare buffered to lower the drive requirement, which significantly reduces the loading on (current required by) clock drivers, for long parallel words. Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output () produces a low-level output pulse under those same conditions, but only while the clock input is low. The counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count (MAX/MIN) output can be used to accomplish look ahead for high-speed operation. The SN54ALS191A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS191A is characterized for operation from 0°C to 70°C. The 'ALS191A are synchronous 4-bit reversible up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the count enable () input is low. A high atinhibits counting. The direction of the count is determined by the level of the down/up (D/U\) input. When D/U\ is low, the counter counts up, and when D/U\ is high, the counter counts down. These counters feature a fully independent clock circuit. Changes at the control inputs (and D/U\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the conditions meeting the stable setup and hold times. These counters are fully programmable. Each output can be preset to either level by placing a low on theinput and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. CLK, D/U\, andare buffered to lower the drive requirement, which significantly reduces the loading on (current required by) clock drivers, for long parallel words. Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output () produces a low-level output pulse under those same conditions, but only while the clock input is low. The counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count (MAX/MIN) output can be used to accomplish look ahead for high-speed operation. The SN54ALS191A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS191A is characterized for operation from 0°C to 70°C.

The 'ALS193A are synchronous, reversible, 4-bit up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count/clock (UP or DOWN) input. The direction of the count is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load () input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent of the count andi nputs. The UP, DOWN, andinputs are buffered to lower the drive requirement, which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words. These counters are designed to be cascaded without the need for external circuitry. The borrow () output produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the carry (CO\) output produces a low-level pulse while the count is 9 or 15 (all Q outputs high) and the UP input is low. The counters can then be easily cascaded by feedingandto the count-down and count-up inputs, respectively, of the succeeding counter. The SN54ALS193A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS193A is characterized for operation from 0°C to 70°C. The 'ALS193A are synchronous, reversible, 4-bit up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. The outputs of the four flip-flops are triggered on a low-to-high-level transition of either count/clock (UP or DOWN) input. The direction of the count is determined by which count input is pulsed while the other count input is high. All four counters are fully programmable; that is, each output may be preset to either level by placing a low on the load () input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A high level applied to the clear (CLR) input forces all outputs to the low level. The clear function is independent of the count andi nputs. The UP, DOWN, andinputs are buffered to lower the drive requirement, which significantly reduces the loading on, or current required by, clock drivers, etc., for long parallel words. These counters are designed to be cascaded without the need for external circuitry. The borrow () output produces a low-level pulse while the count is zero (all Q outputs low) and the DOWN input is low. Similarily, the carry (CO\) output produces a low-level pulse while the count is 9 or 15 (all Q outputs high) and the UP input is low. The counters can then be easily cascaded by feedingandto the count-down and count-up inputs, respectively, of the succeeding counter. The SN54ALS193A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS193A is characterized for operation from 0°C to 70°C.

These devices contain two independent 4-input positive-NAND gates. They perform the Boolean functionsor\ in positive logic. The SN54ALS20A and SN54AS20 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS20A and SN74AS20 are characterized for operation from 0°C to 70°C. These devices contain two independent 4-input positive-NAND gates. They perform the Boolean functionsor\ in positive logic. The SN54ALS20A and SN54AS20 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS20A and SN74AS20 are characterized for operation from 0°C to 70°C.

These devices contain two independent 4-input positive-AND gates. They perform the Boolean functionsorin positive logic. The SN54ALS21A and SN54AS21 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS21A and SN74AS21 are characterized for operation from 0°C to 70°C. These devices contain two independent 4-input positive-AND gates. They perform the Boolean functionsorin positive logic. The SN54ALS21A and SN54AS21 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS21A and SN74AS21 are characterized for operation from 0°C to 70°C.

These octal buffers/drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. When these devices are used with the ’ALS241, ’AS241A, ’ALS244, and ’AS244A devices, the circuit designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs. These devices feature high fan-out and improved fan-in. The -1 version of SN74ALS240A is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS240A. These octal buffers/drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. When these devices are used with the ’ALS241, ’AS241A, ’ALS244, and ’AS244A devices, the circuit designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs. These devices feature high fan-out and improved fan-in. The -1 version of SN74ALS240A is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS240A.

These octal buffers/drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. These devices feature high fan-out and improved fan-in. The -1 version of SN74ALS241C is identical to the standard version, except that the recommended maximum IOLof the -1 version is 48 mA. There is no -1 version of the SN54ALS241C. The SN54ALS241C and SN54AS241A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS241C and SN74AS241A are characterized for operation from 0°C to 70°C. These octal buffers/drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. These devices feature high fan-out and improved fan-in. The -1 version of SN74ALS241C is identical to the standard version, except that the recommended maximum IOLof the -1 version is 48 mA. There is no -1 version of the SN54ALS241C. The SN54ALS241C and SN54AS241A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS241C and SN74AS241A are characterized for operation from 0°C to 70°C.

These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the ´ALS240A, ´ALS241C, ´AS240A, and ´AS241A, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. The -1 version of SN74ALS244C is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS244C. The SN54ALS244C and SN54AS244A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS244C and SN74AS244A are characterized for operation from 0°C to 70°C. These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the ´ALS240A, ´ALS241C, ´AS240A, and ´AS241A, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. The -1 version of SN74ALS244C is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS244C. The SN54ALS244C and SN54AS244A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS244C and SN74AS244A are characterized for operation from 0°C to 70°C.

These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated. The -1 version of the SN74ALS245A is identical to the standard version, except that the recommended maximum IOLis increased to 48 mA. There is no -1 version of the SN54ALS245A. These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so that the buses are effectively isolated. The -1 version of the SN74ALS245A is identical to the standard version, except that the recommended maximum IOLis increased to 48 mA. There is no -1 version of the SN54ALS245A.