Texas Instruments

These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C. These devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset () or clear () inputs sets or resets the outputs, regardless of the levels of the other inputs. Whenandare inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high. The SN54ALS112A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS112A is characterized for operation from 0°C to 70°C.

These devices contain three independent 3-input positive-AND gates. They perform the Boolean functions Y = A • B • C or Y = (A\ + B\ + C\)\ in positive logic. These devices contain three independent 3-input positive-AND gates. They perform the Boolean functions Y = A • B • C or Y = (A\ + B\ + C\)\ in positive logic.

These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable () input can be used to disable the device so the buses are effectively isolated. The SN54ALS1245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS1245A is characterized for operation from 0°C to 70°C. These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable () input can be used to disable the device so the buses are effectively isolated. The SN54ALS1245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS1245A is characterized for operation from 0°C to 70°C.

These devices contain a 13-input positive-NAND gate. They perform the following Boolean functions in positive logic: Y=A\+B\+C\+D\+E\+F\+G\+H\+I\+J\+K\+L\+M\ The SN54ALS133 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS133 is characterized for operation from 0°C to 70°C. These devices contain a 13-input positive-NAND gate. They perform the following Boolean functions in positive logic: Y=A\+B\+C\+D\+E\+F\+G\+H\+I\+J\+K\+L\+M\ The SN54ALS133 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS133 is characterized for operation from 0°C to 70°C.

The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/demultiplexers with latches on the three address inputs. When the latch-enable () input is low, the devices act as decoders/demultiplexers. Whengoes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long asremains high. The output-enable controls (G1 and G2\) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2\ is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems. The SN54ALS137A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS137A and SN74AS137 are characterized for operation from 0°C to 70°C. The SN54ALS137A, SN74ALS137A, and SN74AS137 are 3-line to 8-line decoders/demultiplexers with latches on the three address inputs. When the latch-enable () input is low, the devices act as decoders/demultiplexers. Whengoes from low to high, the address present at the select (A, B, and C) inputs is stored in the latches. Further address changes are ignored as long asremains high. The output-enable controls (G1 and G2\) control the outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2\ is high. These devices are ideally suited for implementing glitch-free decoders in strobed (stored-address) applications in bus-oriented systems. The SN54ALS137A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS137A and SN74AS137 are characterized for operation from 0°C to 70°C.

The ´ALS138A and ´AS138 are 3-line to 8-line decoders/demultiplexers designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance systems, these devices can be used to minimize the effects of system decoding. When employed with high-speed memories with a fast enable circuit, the delay times of the decoder and the enable time of the memory are usually less than the typical access time of the memory. The effective system delay introduced by the Schottky-clamped system decoder is negligible. The conditions at the binary-select (A, B, and C) inputs and the three enable (G1,, and) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN54ALS138A and SN54AS138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS138A and SN74AS138 are characterized for operation from 0°C to 70°C. The ´ALS138A and ´AS138 are 3-line to 8-line decoders/demultiplexers designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance systems, these devices can be used to minimize the effects of system decoding. When employed with high-speed memories with a fast enable circuit, the delay times of the decoder and the enable time of the memory are usually less than the typical access time of the memory. The effective system delay introduced by the Schottky-clamped system decoder is negligible. The conditions at the binary-select (A, B, and C) inputs and the three enable (G1,, and) inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. The SN54ALS138A and SN54AS138 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS138A and SN74AS138 are characterized for operation from 0°C to 70°C.

The ´ALS139 are dual 2-line to 4-line decoders/demultiplexers designed for use in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these devices can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast-enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. Therefore, the effective system delay introduced by the Schottky-clamped system decoder is negligible. The ´ALS139 comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G\) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and simplify system design. The SN54ALS139 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS139 is characterized for operation from 0°C to 70°C. The ´ALS139 are dual 2-line to 4-line decoders/demultiplexers designed for use in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these devices can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast-enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. Therefore, the effective system delay introduced by the Schottky-clamped system decoder is negligible. The ´ALS139 comprise two individual 2-line to 4-line decoders in a single package. The active-low enable (G\) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and simplify system design. The SN54ALS139 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS139 is characterized for operation from 0°C to 70°C.

These data selectors/multiplexers provide full binary decoding to select one-of-eight data sources. The strobe (G\) input must be at a low logic level to enable the inputs. A high level at the strobe terminal forces the W output high and the Y output low. The SN54ALS151 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS151 and SN74AS151 are characterized for operation from 0°C to 70°C. These data selectors/multiplexers provide full binary decoding to select one-of-eight data sources. The strobe (G\) input must be at a low logic level to enable the inputs. A high level at the strobe terminal forces the W output high and the Y output low. The SN54ALS151 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS151 and SN74AS151 are characterized for operation from 0°C to 70°C.

These dual 1-of-4 data selectors/multiplexers contain inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G\) inputs are provided for each of the two 4-line sections. The SN54ALS153 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS153 and SN74AS153 are characterized for operation from 0°C to 70°C. These dual 1-of-4 data selectors/multiplexers contain inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G\) inputs are provided for each of the two 4-line sections. The SN54ALS153 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS153 and SN74AS153 are characterized for operation from 0°C to 70°C.

One of the main applications of the SN74ALS156 is as a dual 1-line to 4-line decoder/demultiplexer with individual strobes (G\) and common binary-address inputs in a single 16-pin package. When both sections are enabled, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit enabling or disabling each of the 4-bit sections, as desired. Data applied to input 1C is inverted at its outputs and data applied at input 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use of the SN74ALS156 as a 3-line to 8-line demultiplexer without external gating. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and simplify system design. The SN74ALS156 is characterized for operation from 0°C to 70°C. One of the main applications of the SN74ALS156 is as a dual 1-line to 4-line decoder/demultiplexer with individual strobes (G\) and common binary-address inputs in a single 16-pin package. When both sections are enabled, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit enabling or disabling each of the 4-bit sections, as desired. Data applied to input 1C is inverted at its outputs and data applied at input 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use of the SN74ALS156 as a 3-line to 8-line demultiplexer without external gating. All inputs are clamped with high-performance Schottky diodes to suppress line ringing and simplify system design. The SN74ALS156 is characterized for operation from 0°C to 70°C.