Texas Instruments

The SN65LBC182 and SN75LBC182 are differential data line transceivers with a high level of ESD protection in the trade-standard footprint of the SN75176. They are designed for balanced transmission lines and meet ANSI standard TIA/EIA-485-A and ISO 8482. The SN65LBC182 and SN75LBC182 combine a 3-state, differential line driver and differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can be externally connected together to function as a direction control. The driver outputs and the receiver inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus. This port operates over a wide range of common-mode voltage, making the device suitable for party-line applications. The device also includes additional features for party-line data buses in electrically noisy environment applications such as industrial process control or power inverters. The SN75LBC182 and SN65LBC182 bus pins also exhibit a high input resistance equivalent to one-fourth unit load allowing connection of up to 128 similar devices on the bus. The high ESD tolerance protects the device for cabled connections. (For an even higher level of protection, see the SN65/75LBC184, literature number SLLS236.) The differential driver design incorporates slew-rate-controlled outputs sufficient to transmit data up to 250 kbps. Slew-rate control allows longer unterminated cable runs and longer stub lengths from the main backbone than possible with uncontrolled voltage transitions. The receiver design provides a fail-safe output of a high level when the inputs are left floating (open circuit). Very low device supply current can be achieved by disabling the driver and the receiver. The SN65LBC182 is characterized for operation from −40°C to 85°C, and the SN75LBC182 is characterized for operation from 0°C to 70°C. The SN65LBC182 and SN75LBC182 are differential data line transceivers with a high level of ESD protection in the trade-standard footprint of the SN75176. They are designed for balanced transmission lines and meet ANSI standard TIA/EIA-485-A and ISO 8482. The SN65LBC182 and SN75LBC182 combine a 3-state, differential line driver and differential input line receiver, both of which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables, respectively, which can be externally connected together to function as a direction control. The driver outputs and the receiver inputs connect internally to form a differential input/output (I/O) bus port that is designed to offer minimum loading to the bus. This port operates over a wide range of common-mode voltage, making the device suitable for party-line applications. The device also includes additional features for party-line data buses in electrically noisy environment applications such as industrial process control or power inverters. The SN75LBC182 and SN65LBC182 bus pins also exhibit a high input resistance equivalent to one-fourth unit load allowing connection of up to 128 similar devices on the bus. The high ESD tolerance protects the device for cabled connections. (For an even higher level of protection, see the SN65/75LBC184, literature number SLLS236.) The differential driver design incorporates slew-rate-controlled outputs sufficient to transmit data up to 250 kbps. Slew-rate control allows longer unterminated cable runs and longer stub lengths from the main backbone than possible with uncontrolled voltage transitions. The receiver design provides a fail-safe output of a high level when the inputs are left floating (open circuit). Very low device supply current can be achieved by disabling the driver and the receiver. The SN65LBC182 is characterized for operation from −40°C to 85°C, and the SN75LBC182 is characterized for operation from 0°C to 70°C.

The SN75LBC184 and SN65LBC184 devices are differential data line transceivers in the trade-standard footprint of the SN75176 with built-in protection against high-energy noise transients. This feature provides a substantial increase in reliability for better immunity to noise transients coupled to the data cable over most existing devices. Use of these circuits provides a reliable low-cost direct-coupled (with no isolation transformer) data line interface without requiring any external components. The SN75LBC184 and SN65LBC184 can withstand overvoltage transients of 400W peak (typical). The conventional combination wave called out in IEC 61000-4-5 simulates the overvoltage transient and models a unidirectional surge caused by overvoltages from switching and secondary lightning transients. The SN75LBC184 and SN65LBC184 devices are differential data line transceivers in the trade-standard footprint of the SN75176 with built-in protection against high-energy noise transients. This feature provides a substantial increase in reliability for better immunity to noise transients coupled to the data cable over most existing devices. Use of these circuits provides a reliable low-cost direct-coupled (with no isolation transformer) data line interface without requiring any external components. The SN75LBC184 and SN65LBC184 can withstand overvoltage transients of 400W peak (typical). The conventional combination wave called out in IEC 61000-4-5 simulates the overvoltage transient and models a unidirectional surge caused by overvoltages from switching and secondary lightning transients.

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of -55°C to 125°C. The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of -55°C to 125°C.

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C. The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.

The SN65LVCP1412 is an asynchronous, protocol-agnostic, low latency, two-channel linear equalizer optimized for use up to 14.2Gbps and compensates for losses in backplane or active cable applications. The architecture of SN65LVCP1412 is designed to work with an ASIC or a FPGA with digital equalization employing Decision Feedback Equalizers (DFE). SN65LVCP1412 linear equalizer preserves the shape of the transmitted signal ensuring optimum DFE performance. SN65LVCP1412 provides a low power solution while at the same time extending the effectiveness of DFE. SN65LVCP1412 is configurable via I2C or GPIO interface. Using the I2C interface of the SN65LVCP1412 enables the user to control independently the Equalization, Path Gain, and Output Dynamic Range for each individual channel. In GPIO mode, Equalization, Path Gain, and Output Dynamic Range can be set for all channels using the GPIO Input pins. SN65LVCP1412 outputs can be disabled independently via I2C. The SN65LVCP1412 operates from a single 2.5V or 3.3V power supply. The package for the SN65LVCP1412 is a 24 pin 4mm x 5mm x 0.75mm QFN (Quad Flatpack, No-lead) lead-free package with 0.5mm pitch, and characterized for operation from –40°C to 85°C. The SN65LVCP1412 is an asynchronous, protocol-agnostic, low latency, two-channel linear equalizer optimized for use up to 14.2Gbps and compensates for losses in backplane or active cable applications. The architecture of SN65LVCP1412 is designed to work with an ASIC or a FPGA with digital equalization employing Decision Feedback Equalizers (DFE). SN65LVCP1412 linear equalizer preserves the shape of the transmitted signal ensuring optimum DFE performance. SN65LVCP1412 provides a low power solution while at the same time extending the effectiveness of DFE. SN65LVCP1412 is configurable via I2C or GPIO interface. Using the I2C interface of the SN65LVCP1412 enables the user to control independently the Equalization, Path Gain, and Output Dynamic Range for each individual channel. In GPIO mode, Equalization, Path Gain, and Output Dynamic Range can be set for all channels using the GPIO Input pins. SN65LVCP1412 outputs can be disabled independently via I2C. The SN65LVCP1412 operates from a single 2.5V or 3.3V power supply. The package for the SN65LVCP1412 is a 24 pin 4mm x 5mm x 0.75mm QFN (Quad Flatpack, No-lead) lead-free package with 0.5mm pitch, and characterized for operation from –40°C to 85°C.

The SN65LVCP1414 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for use up to 14.2Gbps and compensates for losses in backplane or active cable applications. The architecture of the SN65LVCP1414 is designed to work with an ASIC or FPGA with digital equalization employing Decision Feedback Equalizers (DFE). The SN65LVCP1414 linear equalizer preserves the shape of the transmitted signal ensuring optimum DFE performance. The SN65LVCP1414 provides a low power solution while at the same time extending the effectiveness of DFE. The SN65LVCP1414 is configurable via I2C or GPIO interface. Using the I2C interface of the SN65LVCP1414 enables the user to control independently the Equalization, Path Gain, and Output Dynamic Range for each individual channel. In GPIO mode, Equalization, Path Gain, and Output Dynamic Range can be set for all channels using the GPIO Input pins. The SN65LVCP1414 outputs can be disabled independently via I2C. The SN65LVCP1414 operates from a single 2.5V or 3.3V power supply. The package for the SN65LVCP1414 is a 38 pin 5-mm × 7-mm × 0.75-mm QFN (Quad Flat-pack No-lead) lead-free package with 0.5mm pitch and is characterized for operation from –40°C to 85°C. The SN65LVCP1414 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for use up to 14.2Gbps and compensates for losses in backplane or active cable applications. The architecture of the SN65LVCP1414 is designed to work with an ASIC or FPGA with digital equalization employing Decision Feedback Equalizers (DFE). The SN65LVCP1414 linear equalizer preserves the shape of the transmitted signal ensuring optimum DFE performance. The SN65LVCP1414 provides a low power solution while at the same time extending the effectiveness of DFE. The SN65LVCP1414 is configurable via I2C or GPIO interface. Using the I2C interface of the SN65LVCP1414 enables the user to control independently the Equalization, Path Gain, and Output Dynamic Range for each individual channel. In GPIO mode, Equalization, Path Gain, and Output Dynamic Range can be set for all channels using the GPIO Input pins. The SN65LVCP1414 outputs can be disabled independently via I2C. The SN65LVCP1414 operates from a single 2.5V or 3.3V power supply. The package for the SN65LVCP1414 is a 38 pin 5-mm × 7-mm × 0.75-mm QFN (Quad Flat-pack No-lead) lead-free package with 0.5mm pitch and is characterized for operation from –40°C to 85°C.

The SN65LVCP15 is a high performance serial link mux for use in Fibre Channel (1.0625 Gb/s), Gigabit Ethernet (1.25 Gb/s), and other high speed interface applications. A common application involves a serializer/deserializer (SerDes), such as the TLK2201B, which would normally be connected to the IN± and OUT± ports in order to provide duplicate set of links on the IN0/OUT0 and IN1/OUT1 ports. This type of application is often used to implement high speed test ports that can be monitored without affecting the serial data stream of the application. A popular application is in Line Cards, that use serial links from a SerDes like TLK2201B (SLLS585), where the SN65LVCP15 provides redundant, hot-swappable links to redundant Switch Fabric Cards. During normal operation, IN is sent to both OUT0 and OUT1 whose buffers are enabled when OE0 and OE1 are HIGH. OUT0 can select between IN and IN1. OUT1 can select between IN and IN0. OUT can select between IN0 and IN1. In Link Replicator applications, such as the Line Card to Switch Card links, IN is transmitted to both OUT0 and OUT1 which either IN0 or IN1 is selected at OUT. In host Adapter applications, IN goes to OUT0 (an internal connector) which returns data and IN0. IN0 is looped to OUT1 (an external connector) which returns data on IN1 and then back to the SerDes on OUT. The SN65LVCP15 is a high performance serial link mux for use in Fibre Channel (1.0625 Gb/s), Gigabit Ethernet (1.25 Gb/s), and other high speed interface applications. A common application involves a serializer/deserializer (SerDes), such as the TLK2201B, which would normally be connected to the IN± and OUT± ports in order to provide duplicate set of links on the IN0/OUT0 and IN1/OUT1 ports. This type of application is often used to implement high speed test ports that can be monitored without affecting the serial data stream of the application. A popular application is in Line Cards, that use serial links from a SerDes like TLK2201B (SLLS585), where the SN65LVCP15 provides redundant, hot-swappable links to redundant Switch Fabric Cards. During normal operation, IN is sent to both OUT0 and OUT1 whose buffers are enabled when OE0 and OE1 are HIGH. OUT0 can select between IN and IN1. OUT1 can select between IN and IN0. OUT can select between IN0 and IN1. In Link Replicator applications, such as the Line Card to Switch Card links, IN is transmitted to both OUT0 and OUT1 which either IN0 or IN1 is selected at OUT. In host Adapter applications, IN goes to OUT0 (an internal connector) which returns data and IN0. IN0 is looped to OUT1 (an external connector) which returns data on IN1 and then back to the SerDes on OUT.

The SN65LVCP202 is a 2 × 2 nonblocking crosspoint switch in a flow-through pinout allowing for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 2:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve high signaling speeds while maintaining low signal skews. The SN65LVCP202 incorporates 100-termination resistors for those applications where board space is at a premium. Transmit preemphasis and receive equalization are built in for superior signal integrity performance. The SN65LVCP202 is characterized for operation from –40°C to 85°C. The SN65LVCP202 is a 2 × 2 nonblocking crosspoint switch in a flow-through pinout allowing for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 2:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve high signaling speeds while maintaining low signal skews. The SN65LVCP202 incorporates 100-termination resistors for those applications where board space is at a premium. Transmit preemphasis and receive equalization are built in for superior signal integrity performance. The SN65LVCP202 is characterized for operation from –40°C to 85°C.

The SN65LVCP204 is a 4×4 non-blocking crosspoint switch in a flow-through pinout that allows for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve high signaling speeds while maintaining low signal skews. The SN65LVCP204 incorporates 100-termination resistors for those applications where board space is at a premium. Transmit preemphasis and receive equalization are built in for superior signal integrity performance. The SN65LVCP204 is a 4×4 non-blocking crosspoint switch in a flow-through pinout that allows for ease in PCB layout. VML signaling is used to achieve a high-speed data throughput while using low power. Each of the output drivers includes a 4:1 multiplexer to allow any input to be routed to any output. Internal signal paths are fully differential to achieve high signaling speeds while maintaining low signal skews. The SN65LVCP204 incorporates 100-termination resistors for those applications where board space is at a premium. Transmit preemphasis and receive equalization are built in for superior signal integrity performance.

The SN65LVCP22 is a 2x2 crosspoint switch providing greater than 1000 Mbps operation for each path. The dual channels incorporate wide common-mode (0 V to 4 V) receivers, allowing for the receipt of LVDS, LVPECL, and CML signals. The dual outputs are LVDS drivers to provide low-power, low-EMI, high-speed operation. The SN65LVCP22 provides a single device supporting 2:2 buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2x2 switching, and LVPECL/CML to LVDS level translation on each channel. The flexible operation of the SN65LVCP22 provides a single device to support the redundant serial bus transmission needs (working and protection switching cards) of fault–tolerant switch systems found in optical networking, wireless infrastructure, and data communications systems. TI offers additional gigibit repeater/translator and crosspoint products in the SN65LVDS100 and SN65LVDS122. The SN65LVCP22 uses a fully differential data path to ensure low-noise generation, fast switching times, low pulse width distortion, and low jitter. Output channel-to-channel skew is less than 10 ps (typ) and 50 ps (max) to ensure accurate alignment of outputs in all applications. Both SOIC and TSSOP package options are available to allow easy upgrade for existing solutions, and board area savings where space is critical. The SN65LVCP22 is a 2x2 crosspoint switch providing greater than 1000 Mbps operation for each path. The dual channels incorporate wide common-mode (0 V to 4 V) receivers, allowing for the receipt of LVDS, LVPECL, and CML signals. The dual outputs are LVDS drivers to provide low-power, low-EMI, high-speed operation. The SN65LVCP22 provides a single device supporting 2:2 buffering (repeating), 1:2 splitting, 2:1 multiplexing, 2x2 switching, and LVPECL/CML to LVDS level translation on each channel. The flexible operation of the SN65LVCP22 provides a single device to support the redundant serial bus transmission needs (working and protection switching cards) of fault–tolerant switch systems found in optical networking, wireless infrastructure, and data communications systems. TI offers additional gigibit repeater/translator and crosspoint products in the SN65LVDS100 and SN65LVDS122. The SN65LVCP22 uses a fully differential data path to ensure low-noise generation, fast switching times, low pulse width distortion, and low jitter. Output channel-to-channel skew is less than 10 ps (typ) and 50 ps (max) to ensure accurate alignment of outputs in all applications. Both SOIC and TSSOP package options are available to allow easy upgrade for existing solutions, and board area savings where space is critical.