SN65LV1023A-EP Series

Enhanced product 10:1 LVDS SerDes transmitter 100 to 660-Mbps

Catalog

Enhanced product 10:1 LVDS SerDes transmitter 100 to 660-Mbps

Part	Number of Inputs	Supplier Device Package	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Input Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Function	Data Rate	Number of Outputs	Package / Case [custom]	Package / Case [custom]	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments SN65LV1023ARHBT	10	32-VQFN (5x5)	LVDS	85 °C	-40 °C	Surface Mount	LVTTL	3.6 V	3 V	32-VFQFN Exposed Pad	Serializer	660 Mbps	1
Texas Instruments SN65LV1023ARHBR	10	32-VQFN (5x5)	LVDS	85 °C	-40 °C	Surface Mount	LVTTL	3.6 V	3 V	32-VFQFN Exposed Pad	Serializer	660 Mbps	1
Texas Instruments SN65LV1023ADBR	10	28-SSOP	LVDS	85 °C	-40 °C	Surface Mount	LVTTL	3.6 V	3 V	28-SSOP	Serializer	660 Mbps	1	0.209 in	5.3 mm
Texas Instruments SN65LV1023ADB	10	28-SSOP	LVDS	85 °C	-40 °C	Surface Mount	LVTTL	3.6 V	3 V	28-SSOP	Serializer	660 Mbps	1	0.209 in	5.3 mm
Texas Instruments SN65LV1023AMDBREP	10	28-SSOP	LVDS			Surface Mount	LVTTL	3.6 V	3 V	28-SSOP	Serializer	660 Mbps	1	0.209 in	5.3 mm	125 °C	-55 °C

Catalog

Enhanced product 10:1 LVDS SerDes transmitter 100 to 660-Mbps

Key Features

• Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of -55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 66-MHz System ClockPin-Compatible Superset of DS92LV1023/DS92LV1224Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHzSynchronization Mode for Faster LockLock IndicatorNo External Components Required for PLL28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages AvailableProgrammable Edge Trigger on ClockFlow-Through Pinout for Easy PCB Layout(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Controlled BaselineOne Assembly/Test Site, One Fabrication SiteExtended Temperature Performance of -55°C to 125°CEnhanced Diminishing Manufacturing Sources (DMS) SupportEnhanced Product-Change NotificationQualification Pedigree(1)100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz to 66-MHz System ClockPin-Compatible Superset of DS92LV1023/DS92LV1224Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHzSynchronization Mode for Faster LockLock IndicatorNo External Components Required for PLL28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages AvailableProgrammable Edge Trigger on ClockFlow-Through Pinout for Easy PCB Layout(1)Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Description

The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of -55°C to 125°C. The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput. Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters. The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock. The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of -55°C to 125°C.