Texas Instruments

The SN54AC02-DIE device contains four independent 2-input NOR gates that perform the Boolean function Y =A•Bor Y =A + Bin positive logic. The SN54AC02-DIE device contains four independent 2-input NOR gates that perform the Boolean function Y =A•Bor Y =A + Bin positive logic.

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The SN54ACT16244 and 74ACT16244 are 16-bit buffers/line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. They can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide true outputs and symmetrical(active-low) output-enable inputs. The 74ACT16244 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ACT16244 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16244 is characterized for operation from -40°C to 85°C. The SN54ACT16244 and 74ACT16244 are 16-bit buffers/line drivers designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. They can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The devices provide true outputs and symmetrical(active-low) output-enable inputs. The 74ACT16244 is packaged in TI's shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The SN54ACT16244 is characterized for operation over the full military temperature range of -55°C to 125°C. The 74ACT16244 is characterized for operation from -40°C to 85°C.

These SNx4ACT244 octal buffers and drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SNx4ACT244 devices are organized as two 4-bit buffers and drivers with separate output-enable (OE) inputs. When OE is low, the device passes non-inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. These SNx4ACT244 octal buffers and drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SNx4ACT244 devices are organized as two 4-bit buffers and drivers with separate output-enable (OE) inputs. When OE is low, the device passes non-inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

These SNx4ACT244 octal buffers and drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SNx4ACT244 devices are organized as two 4-bit buffers and drivers with separate output-enable (OE) inputs. When OE is low, the device passes non-inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. These SNx4ACT244 octal buffers and drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SNx4ACT244 devices are organized as two 4-bit buffers and drivers with separate output-enable (OE) inputs. When OE is low, the device passes non-inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

The ’AC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The ’AC245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths. The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The input-ready (IRA, IRB) flag and almost-full (AFA\, AFB\) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA\, AEB\) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the almost-full and almost-empty flags of both FIFOs can be programmed from port A. The SN54ACT3632 is characterized for operation over the full military temperature range of -55°C to 125°C. For more information on this device family, see the following application reports: The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths. The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The input-ready (IRA, IRB) flag and almost-full (AFA\, AFB\) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA\, AEB\) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the almost-full and almost-empty flags of both FIFOs can be programmed from port A. The SN54ACT3632 is characterized for operation over the full military temperature range of -55°C to 125°C. For more information on this device family, see the following application reports:

These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. These 8-bit latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The 'ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of complex circuit-board assemblies. The 'ACT8990 differ from other SCOPETMintegrated circuits. Their function is to control the JTAG serial-test bus rather than being target boundary-scannable devices. The required signals of the JTAG serial-test bus - test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s), and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI, and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits. Since the TBC can be configured to generate up to six separate TMS signals [TMS (5-0)], it can be used to control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO signals). While most operations of the TBC are synchronous to TCKI, a test-off (TOFF\) input is provided for output control of the target interface, and a test-reset (TRST\) input is provided for hardware/software reset of the TBC. In addition, four event [EVENT (3-0)] I/Os are provided for asynchronous communication to target device(s). Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit counters. The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus [ADRS (4-0)] and the 16-bit read/write data bus [DATA (15-0)]. Read (RD\) and write (WR\) strobes are implemented such that the critical host-interface timing is independent of the TCKI period. Any one of 24 registers can be addressed for read and/or write operations. In addition to control and status registers, the TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the host via ready (RDY\) and interrupt (INT\) outputs. Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A 32-bit counter can be preset to allow a predetermined number of execution or scan operations. Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO output is written by the host to the write buffer. The SN54ACT8990 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8990 is characterized for operation from 0°C to 70°C. NC - No internal connection The 'ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPETMtestability integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary scan to facilitate testing of complex circuit-board assemblies. The 'ACT8990 differ from other SCOPETMintegrated circuits. Their function is to control the JTAG serial-test bus rather than being target boundary-scannable devices. The required signals of the JTAG serial-test bus - test clock (TCK), test mode select (TMS), test data input (TDI), and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s), and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI, and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits. Since the TBC can be configured to generate up to six separate TMS signals [TMS (5-0)], it can be used to control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO signals). While most operations of the TBC are synchronous to TCKI, a test-off (TOFF\) input is provided for output control of the target interface, and a test-reset (TRST\) input is provided for hardware/software reset of the TBC. In addition, four event [EVENT (3-0)] I/Os are provided for asynchronous communication to target device(s). Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit counters. The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus [ADRS (4-0)] and the 16-bit read/write data bus [DATA (15-0)]. Read (RD\) and write (WR\) strobes are implemented such that the critical host-interface timing is independent of the TCKI period. Any one of 24 registers can be addressed for read and/or write operations. In addition to control and status registers, the TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the host via ready (RDY\) and interrupt (INT\) outputs. Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A 32-bit counter can be preset to allow a predetermined number of execution or scan operations. Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO output is written by the host to the write buffer. The SN54ACT8990 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ACT8990 is characterized for operation from 0°C to 70°C. NC - No internal connection

The ’AHC123A devices are dual retriggerable monostable multivibrators designed for 2V to 5.5V VCC operation. The ’AHC123A devices are dual retriggerable monostable multivibrators designed for 2V to 5.5V VCC operation.