Analog Devices

The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight.ApplicationsCommunicationsDiversity multi-band, multi-mode digital receivers3G/4G, TD-SCDMA, WCDMA, MC-GSM, LTEGeneral-purpose software radiosUltrawideband satellite receiverInstrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)RadarDigital oscilloscopesHigh speed data acquisition systemsDOCSIS CMTS upstream receive pathsHFC digital reverse path receivers

The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9689 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation rates. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9689 between the DDC modes is selectable via SPI-programmable profiles.In addition to the DDC blocks, the AD9689 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9689 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9689 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).The AD9689 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. This product is protected by a U.S. patent.Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.Product HighlightsWide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz.Four integrated, wideband decimation filters and NCO blocks supporting multiband receivers.Fast NCO switching enabled through the GPIO pins.SPI controls various product features and functions to meet specific system requirements.Programmable fast overrange detection and signal monitoring.On-chip temperature diode for system thermal management.12 mm × 12 mm, 196-ball BGA.Pin, package, feature, and memory map compatible with the AD9208 14-bit, 3.0 GSPS, JESD204B dual ADC.ApplicationsDiversity multiband and multimode digital receivers3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-AElectronic test and measurement systemsPhased array radar and electronic warfareDOCSIS 3.0 CMTS upstream receive pathsHFC digital reverse path receivers

The AD9690 is a 14-bit, 1 GSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9690 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. The ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters.In addition to the DDC blocks, the AD9690 has several functions that simplify the automatic gain control (AGC) function in the communications receiver.The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane con-figurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9690 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.p>The AD9690 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product may be protected by one or more U.S. or international patents.Product HighlightsWide full power bandwidth supports IF sampling of signals up to 2 GHz.Buffered inputs with programmable input termination eases filter design and implementation.Two integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.Programmable fast overrange detection.9 mm × 9 mm 64-lead LFCSP.ApplicationsCommunicationsMultiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTEGeneral-purpose software radiosUltrawideband satellite receiversInstrumentationRadarsSignals intelligence (SIGINT)DOCSIS 3.0 CMTS upstream receive pathsHFC digital reverse path receivers

The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed for sampling wide bandwidth analog signals of up to 1.5 GHz.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO) and four half-band decimation filters.In addition to the DDC blocks, the AD9691 has a programmable threshold detector that allows monitoring of the incoming signal power using the fast detect output bits of the ADC. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, four- or eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± input pins.The AD9691 is available in a Pb-free, 88-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.Product HighlightsLow power consumption analog core, 14-bit, 1.25 GSPS dual analog-to-digital converter (ADC) with 1.9 W per channel.Wide full power bandwidth supports IF sampling of signals up to 1.5 GHz.Buffered inputs with programmable input termination eases filter design and implementation.Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.Programmable fast overrange detection.12 mm × 12 mm 88-lead LFCSP.ApplicationsCommunications (wideband receivers and digital predistortion)Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions)DOCSIS 3.x CMTS upstream receive pathsHigh speed data acquisition systems

The AD9694 is a quad, 14-bit, 500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 1.4 GHz. The AD9694 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog inputs and clock signals are differential inputs. Each pair of ADC data outputs is internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters.In addition to the DDC blocks, the AD9694 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.The AD9694 has flexible power-down options that allow significant power savings when desired. All of these features can be pro-grammed using the 1.8 V capable, 3-wire SPI.The AD9694 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range.PRODUCT HIGHLIGHTSLow power consumption per channel.JESD204B lane rate support up to 15 Gbps.Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz.Buffered inputs ease filter design and implementation.Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.Programmable fast overrange detection.On-chip temperature diode for system thermal management.APPLICATIONSCommunicationsDiversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-AGeneral-purpose software radiosUltrawideband satellite receiversInstrumentationRadarsSignals intelligence (SIGINT)

The AD9697 is a single, 14-bit, 1300 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The −3 dB bandwidth of the ADC input is 2 GHz. The AD9697 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/ output (GPIO) pins, or to use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9697 between the DDC modes is selectable via serial port interface (SPI)programmable profiles.In addition to the DDC blocks, the AD9697 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9697 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9697 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire SPI and or PDWN/STBY pin.The AD9697 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +105°C junction temperature (TJ) range. This product may be protected by one or more U.S. or international patents.Note that, throughout this data sheet, a multifunction pin, FD/GPIO1, is referred to either by the entire pin name or by a single function of the pin, for example, FD, when only that function is relevant.Product HighlightsLow power consumptionJESD204B lane rate support up to 16 GbpsWide, full power bandwidth supports intermediate frequency (IF) sampling of signals up to 2 GHzBuffered inputs ease filter design and implementationFour integrated wideband decimation filters and NCO blocks supporting multiband receiversProgrammable fast overrange detectionOn-chip temperature diode for system thermal managementApplicationsCommunicationsDiversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTEGeneral-purpose software radiosUltrawideband satellite receiverInstrumentationOscilloscopesSpectrum analyzersNetwork analyzersIntegrated RF test solutionsRadarsElectronic support measures, electronic counter measures, and electronic counter to counter measuresHigh speed data acquisition systemsDOCSIS 3.0 CMTS upstream receive pathsHybrid fiber coaxial digital reverse path receiversWideband digital predistortion

The AD9699 is a single, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed to support applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9699 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital down-converters (DDCs) through a crossbar multiplexer (mux). Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimation filters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9699 between the DDC modes is selectable via serial peripheral interface (SPI)-programmable profiles.In addition to the DDC blocks, the AD9699 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9699 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.The user can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four-lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multi-device synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9699 has flexible power-down options that allow significant power savings when desired. All of these features can be program-med using a 3-wire SPI.The AD9699 is available in a Pb-free, 12 mm × 12 mm, 196-ball BGA and is specified over the −40°C to +85°C ambient temperature range. This product is protected by a U.S. patent.Note that throughout the data sheet, multifunction pins, such as FD/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD, when only that function is relevant.PRODUCT HIGHLIGHTSWide, input −3 dB bandwidth of 9 GHz supports direct RF sampling of signals up to about 5 GHz.Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers.Fast NCO switching enabled through the GPIO pins.An SPI controls various product features and functions to meet specific system requirements.Programmable fast overrange detection and signal monitoring.On-chip temperature diode for system thermal management.12 mm × 12 mm, 196-ball BGA.APPLICATIONSDiversity multiband and multimode digital receivers3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-AElectronic test and measurement systemsPhased array radar and electronic warfareDOCSIS 3.0 CMTS upstream receive pathsHFC digital reverse path receiversLIDAR

The AD9704/AD9705/AD9706/AD9707are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to-analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/AD9705/AD9706/AD9707 family is pin-compatible with the AD9748/AD9740/AD9742/AD9744 family of TxDAC converters and is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface, LFCSP package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9704/AD9705/AD9706/AD9707 offers exceptional ac and dc performance, while supporting update rates up to 175 MSPS.The flexible power supply operating range of 1.7 V to 3.6 V and low power dissipation of the AD9704/AD9705/AD9706/AD9707 parts make them well suited for portable and low power applications.Power dissipation of the AD9704/AD9705/AD9706/AD9707 can be reduced to 15 mW, with a small trade-off in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 2.2 mW.The AD9704/AD9705/AD9706/AD9707 has an optional serial peripheral interface (SPI®) that provides a higher level of programmability to enhance performance of the DAC. An adjustable output, common-mode feature allows for easy interfacing to other components that require common modes from 0 V to 1.2 V.Edge-triggered input latches and a 1.0 V temperature-compensated band gap reference have been integrated to provide a complete, monolithic DAC solution. The digital inputs support 1.8 V and 3.3 V CMOS logic families.PRODUCT HIGHLIGHTSPin Compatible. The AD9704/AD9705/AD9706/AD9707 line of TxDAC converters is pin-compatible with theAD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP package).Low Power. Complete CMOS DAC operates on a single supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V) and 12 mW (1.8 V). The DAC full-scale current can be reduced for lower power operation. Sleep and power-down modes are provided for low power idle periods.Self-Calibration. Self-calibration enables true 14-bit INL and DNL performance in the AD9707.Twos Complement/Binary Data Coding Support. Data input supports twos complement or straight binary data coding.Flexible Clock Input. A selectable high speed, single-ended,and differential CMOS clock input supports 175 MSPS conversion rate.Device Configuration. Device can be configured through pin strapping, and SPI control offers a higher level of programmability.Easy Interfacing to Other Components. Adjustable common-mode output allows for easy interfacing to other signal chain components that accept common-mode levels from 0 V to 1.2 V.On-Chip Voltage Reference. The AD9704/AD9705/AD9706/AD9707 include a 1.0 V temperature-compensated band gap voltage reference.Industry-Standard 32-Lead LFCSP Package.

TheAD9704/AD9705/AD9706/AD9707are the fourth-generation family in the TxDAC series of high performance, CMOS digital-to-analog converters (DACs). This pin-compatible, 8-/10-/12-/14-bit resolution family is optimized for low power operation, while maintaining excellent dynamic performance. The AD9704/AD9705/AD9706/AD9707 family is pin-compatible with the AD9748/AD9740/AD9742/AD9744 family of TxDAC converters and is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface, LFCSP package, and pinout, providing an upward or downward component selection path based on performance, resolution, and cost. The AD9704/AD9705/AD9706/AD9707 offers exceptional ac and dc performance, while supporting update rates up to 175 MSPS.The flexible power supply operating range of 1.7 V to 3.6 V and low power dissipation of the AD9704/AD9705/AD9706/AD9707 parts make them well suited for portable and low power applications.Power dissipation of the AD9704/AD9705/AD9706/AD9707 can be reduced to 15 mW, with a small trade-off in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 2.2 mW.The AD9704/AD9705/AD9706/AD9707 has an optional serial peripheral interface (SPI®) that provides a higher level of programmability to enhance performance of the DAC. An adjustable output, common-mode feature allows for easy interfacing to other components that require common modes from 0 V to 1.2 V.Edge-triggered input latches and a 1.0 V temperature-compensated band gap reference have been integrated to provide a complete, monolithic DAC solution. The digital inputs support 1.8 V and 3.3 V CMOS logic families.PRODUCT HIGHLIGHTSPin Compatible. The AD9704/AD9705/AD9706/AD9707 line of TxDAC converters is pin-compatible with theAD9748/AD9740/AD9742/AD9744 TxDAC line (LFCSP package).Low Power. Complete CMOS DAC operates on a single supply of 3.6 V down to 1.7 V, consuming 50 mW (3.3 V) and 12 mW (1.8 V). The DAC full-scale current can be reduced for lower power operation. Sleep and power-down modes are provided for low power idle periods.Self-Calibration. Self-calibration enables true 14-bit INL and DNL performance in the AD9707.Twos Complement/Binary Data Coding Support. Data input supports twos complement or straight binary data coding.Flexible Clock Input. A selectable high speed, single-ended,and differential CMOS clock input supports 175 MSPS conversion rate.Device Configuration. Device can be configured through pin strapping, and SPI control offers a higher level of programmability.Easy Interfacing to Other Components. Adjustable common-mode output allows for easy interfacing to other signal chain components that accept common-mode levels from 0 V to 1.2 V.On-Chip Voltage Reference. The AD9704/AD9705/AD9706/AD9707 include a 1.0 V temperature-compensated band gap voltage reference.Industry-Standard 32-Lead LFCSP Package.