Analog Devices

The AD9665 is a laser diode driver for high performance CD-RW and DVD recordable drives. It includes four channels for four different optical power levels: the read channel generates a continuous output power level, whereas Channel 1, Channel 2, and Channel 3 can be used as write channels that can be controlled with an LVDS or TTL interface. The WxDIS andRDISpins are active low logic. The OSCEN pin is controlled by an active high TTL signal. All active channels are summed at the output where Write Channel 1 can contribute at least 325 mA output current, and Write Channel 2 and Write Channel 3 can contribute at least 250 mA and 150 mA, respectively. The level of the output current is set by an external resistor, which converts this voltage into a current at the WxSET pin.An on-chip oscillator is provided to allow output current modulation and to reduce laser-mode hopping. Four external resistors permit the setting of two distinct values for the frequency and swing of the oscillator. The oscillator can output up to 100 mA p-p of current (push-pull oscillator) with a frequency range of 200 MHz to 500 MHz.ApplicationsDVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM supercombo drivesMagneto-optical (MO) drivesLaser diode current switchingOTDR laser drivers

The AD9671 is designed for low cost, low power, small size, and ease of use for medical ultrasound applications. It contains eight channels of a VGA with an LNA, a CW harmonic rejection I/Q demodulator with programmable phase rotation, an AAF, an ADC, and a digital demodulator and decimator for data processing and bandwidth reduction.Each channel features a maximum gain of up to 52 dB, a fully differential signal path, and an active input preamplifier termination. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.The LNA has a single-ended to differential gain that is selectable through the serial port interface (SPI). Assuming a 15 MHz noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is 94 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator that has independently programmable phase rotation with 16 phase settings.Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built-in fixed patterns, built-in pseudorandom patterns, and custom user defined test patterns entered via the SPI.ApplicationsMedical imaging/ultrasoundNondestructive testing (NDT)

The AD9674 is designed for low cost, low power, small size, and ease of use for medical ultrasound. It contains eight channels of a VGA with an LNA, a CW harmonic rejection I/Q demodulator with programmable phase rotation, an AAF, an ADC, a digital HPF, and RF decimation by 2.Each channel features a maximum gain of up to 52 dB, a fully differential signal path, and an active input preamplifier termination. The channel is optimized for high dynamic performance and low power in applications where a small package size is critical.The LNA has a single-ended to differential gain that is selectable through the serial port interface (SPI). Assuming a 15 MHz noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is 94 dB. In CW Doppler mode, each LNA output drives an I/Q demodulator that has independently programmable phase rotation with 16 phase settings.Power-down of individual channels is supported to increase battery life for portable applications. Standby mode allows quick power-up for power cycling. In CW Doppler operation, the VGA, AAF, and ADC are powered down. The ADC contains several features designed to maximize flexibility and minimize system cost, such as a programmable clock, data alignment, and programmable digital test pattern generation. The digital test patterns include built in fixed patterns, built in pseudorandom patterns, and custom user defined test patterns entered via the SPI.ApplicationsMedical imaging/ultrasoundNondestructive Testing (NDT)

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTSWide full power bandwidth supports IF sampling of signals up to 2 GHz.Buffered inputs with programmable input termination eases filter design and implementation.Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.Programmable fast overrange detection.9 mm × 9 mm, 64-lead LFCSP.APPLICATIONSCommunicationsDiversity multiband, multimode digital receivers3G/4G, TD-SCDMA, W-CDMA, GSM, LTEGeneral-purpose software radiosUltrawideband satellite receiversInstrumentationRadarsSignals intelligence (SIGINT)DOCSIS 3.0 CMTS upstream receive pathsHFC digital reverse path receivers

The AD9681 is an octal, 14-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit that is designed for low cost, low power, small size, and ease of use. The device operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and an LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The AD9681 automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. Data clock outputs (DCO±1, DCO±2) for capturing data on the output and frame clock outputs (FCO±1, FCO±2) for signaling a new output byte are provided. Individual channel power-down is supported, and the device typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9681 is available in an RoHS-compliant, 144-ball CSP-BGA. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.Product HighlightsSmall Footprint. Eight ADCs are contained in a small, 10 mm × 10 mm package.Low Power. The device dissipates 110 mW per channel at 125 MSPS with scalable power options.Ease of Use. Data clock outputs (DCO±1, DCO±2) operate at frequencies of up to 500 MHz and support double data rate (DDR) operation.User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.ApplicationMedical imagingCommunications receiversMultichannel data acquisition

The AD9683 is a 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9683 supports communications applications where low cost, small size, wide bandwidth, and versatility are desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC core features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. The ADC output data is routed directly to the JESD204B serial output lane. These outputs are at CML voltage levels. Data can be sent through the lane at the maximum sampling rate of 250 MSPS, which results in a lane rate of 5 Gbps. Synchronization inputs (SYNCINB± and SYSREF±) are provided. Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported via the dedicated fast detect pins. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9683 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.Product HighlightsIntegrated 14-bit, 170 MSPS/250 MSPS ADC.The configurable JESD204B output block supports lane rates up to 5 Gbps.An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.Support for an optional radio frequency (RF) clock input to ease system board design.Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.Operation from a single 1.8 V power supply.Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration.ApplicationsCommunicationsDiversity radio systemsMultimode digital receivers (3G)TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTEDOCSIS 3.0 CMTS upstream receive pathsHFC digital reverse path receiversSmart antenna systemsElectronic test and measurement equipmentRadar receiversCOMSEC radio architecturesIED detection/jamming systemsGeneral-purpose software radiosBroadband data applicationsUltrasound equipment