AD9694 Series

Quad 14-Bit, 500 MSPS, 1.2 V/2.5 V Analog-to-Digital Converter

Catalog

Quad 14-Bit, 500 MSPS, 1.2 V/2.5 V Analog-to-Digital Converter

Part	Architecture	Input Type	Sampling Rate (Per Second)	Package / Case	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Data Interface	Features	Number of Bits	Number of Inputs	Operating Temperature [Min]	Operating Temperature [Max]	Supplier Device Package	Reference Type	Configuration	Number of A/D Converters	Ratio - S/H:ADC	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Mounting Type	Power (Typ) @ Conditions	Input Range	Supplied Contents	Utilized IC / Part
Analog Devices AD9694BCPZ-500	Pipelined	Differential	500 M	72-VFQFN Exposed Pad CSP	1 V	0.95 V	JESD204B	Simultaneous Sampling	14	4	-40 °C	105 ░C	72-LFCSP-VQ (10x10)	Internal	S/H-ADC	4	1:1	0.95 V 1.71 V 2.44 V	1 V 1.89 V 2.56 V	Surface Mount
Analog Devices AD9694BCPZRL7-500	Pipelined	Differential	500 M	72-VFQFN Exposed Pad CSP	1 V	0.95 V	JESD204B	Simultaneous Sampling	14	4	-40 °C	105 ░C	72-LFCSP-VQ (10x10)	Internal	S/H-ADC	4	1:1	0.95 V 1.71 V 2.44 V	1 V 1.89 V 2.56 V	Surface Mount
Analog Devices AD9694-500EBZ			500 M				JESD204B Serial		14							4					1.66 W	1.8 Vpp	Board(s)	AD9694

Catalog

Quad 14-Bit, 500 MSPS, 1.2 V/2.5 V Analog-to-Digital Converter

Key Features

• JESD204B (Subclass 1) coded serial digital outputsLane rates up to 15 Gbps

• Lane rates up to 15 Gbps

• 1.66 W total power at 500 MSPS415 mW per analog-to-digital converter (ADC) channel

• 415 mW per analog-to-digital converter (ADC) channel

• SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range)

• SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range)

• Noise density = −151.5 dBFS/Hz (1.80 V p-p input range)

• 0.975 V, 1.8 V, and 2.5 V dc supply operation

• No missing codes

• Internal ADC voltage reference

• Analog input buffer

• On-chip dithering to improve small signal linearity

• Flexible differential input range1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)

• 1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)

• 1.4 GHz analog input full power bandwidth

• Amplitude detect bits for efficient AGC implementation

• 4 integrated wideband digital processors48-bit NCO, up to 4 cascaded half-band filters

• 48-bit NCO, up to 4 cascaded half-band filters

• Differential clock input

• Integer clock divide by 1, 2, 4, or 8

• On-chip temperature diode

• Flexible JESD204B lane configurations

• DownloadAD9694-EP Data Sheet(pdf)

• Military temperature range (−55°C to +105°C)

• Controlled manufacturing baseline

• 1 assembly/test site

• 1 fabrication site

• Product change notification

• Qualification data available on request

• V62/23611

Description

The AD9694 is a quad, 14-bit, 500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 1.4 GHz. The AD9694 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The quad ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog inputs and clock signals are differential inputs. Each pair of ADC data outputs is internally connected to two DDCs through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator, NCO, and up to four half-band decimation filters.In addition to the DDC blocks, the AD9694 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure each pair of intermediate frequency (IF) receiver outputs onto either one or two lanes of Subclass 1 JESD204B-based high speed serialized outputs, depending on the decimation ratio and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.The AD9694 has flexible power-down options that allow significant power savings when desired. All of these features can be pro-grammed using the 1.8 V capable, 3-wire SPI.The AD9694 is available in a Pb-free, 72-lead LFCSP and is specified over the −40°C to +105°C junction temperature range.PRODUCT HIGHLIGHTSLow power consumption per channel.JESD204B lane rate support up to 15 Gbps.Wide full power bandwidth supports IF sampling of signals up to 1.4 GHz.Buffered inputs ease filter design and implementation.Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.Programmable fast overrange detection.On-chip temperature diode for system thermal management.APPLICATIONSCommunicationsDiversity multiband, multimode digital receivers 3G/4G, W-CDMA, GSM, LTE, LTE-AGeneral-purpose software radiosUltrawideband satellite receiversInstrumentationRadarsSignals intelligence (SIGINT)