Analog Devices

The AD9633 is a quad, 12-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9633 is available in a RoHS-compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.ApplicationsMedical ultrasoundHigh speed imagingQuadrature radio receiversDiversity radio receiversTest equipment

The AD9634 is a 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9634 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data are routed directly to the external 12-bit LVDS output port.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire, SPI-compatible serial interface.The AD9634 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTSIntegrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.Fast overrange and threshold detect.Proprietary differential input maintains excellent SNR performance for input frequencies up to 350 MHz.3-pin, 1.8V SPI port for register programming and readback.Pin compatibility with theAD9642, allowing a simple migration up to 14 bits, and with theAD6672.APPLICATIONSCommunicationsDiversity radio systemsMultimode digital receivers (3G)TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTEI/Q demodulation systemsSmart antenna systemsGeneral-purpose software radiosUltrasound equipmentBroadband data applications

The AD9635 is a dual, 12-bit, 80 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported; the AD9635 typically consumes less than 2 mW in the full power-down state. The ADC provides several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9635 is available in a RoHS-compliant, 32-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTSSmall Footprint. Two ADCs are contained in a small, spacesaving package.Low Power. The AD9635 uses 115 mW/channel at 125 MSPS with scalable power options.Pin Compatibility with theAD9645, a 14-Bit Dual ADC.Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation.User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.APPLICATIONSCommunicationsDiversity radio systemsMultimode digital receiversGSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMAI/Q demodulation systemsSmart antenna systemsBroadband data applicationsBattery-powered instrumentsHand held scope metersPortable medical imaging and ultrasoundRadar/LIDAR

The AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 80 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.APPLICATIONSMedical imaging and nondestructive ultrasoundPortable ultrasound and digital beam-forming systemsQuadrature radio receiversDiversity radio receiversOptical networkingTest equipmentPRODUCT HIGHLIGHTSSmall Footprint. Eight ADCs are contained in a small, space-saving package.Low Power of 60 mW/Channel at 80 MSPS with Scalable Power Options.Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 480 MHz and supports double data rate (DDR) operation.User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.Pin Compatible with the AD9257 (14-Bit Octal ADC).

The AD9639 is a quad, 12-bit, 210 MSPS analog-to-digital converter (ADC) with an on-chip temperature sensor and a high speed serial interface. It is designed to support digitizing high frequency, wide dynamic range signals with an input bandwidth up to 780MHz. The output data are serialized per the JESD204 standard. The ADC requires a single 1.8 V power supply and the input clock may be driven differentially with a sine wave, LVPECL, TTL, or LVDS. A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles. The on-chip reference removes the need for external decoupling and can be adjusted by means of SPI control.Various power-down and standby modes are supported. The ADC typically consumes 145 mW per channel with the digital link still in operation when standby operation is enabled.Fabricated on an advanced CMOS process, the AD9639 is available in a Pb free/RoHS compliant, 72-lead LFCSP package. It is specified over the industrial temperature range of −40°C to +85°C.PRODUCT HIGHLIGHTSFour ADCs are contained in a small, space-saving package.On chip PLL allows user to provide one ADC sampling clock and the ADC distributes and multiplies up to produce the corresponding data rate clock.Encoded data rate supports up to 4Gbps per channel. Encoding includes 8B/10B to ensure proper DC common mode and embedded clock per JESD204.The AD9639 operates from a single 1.8 V power supply.APPLICATIONSCommunication receiversCable head end equipment/M-CMTSBroadband radiosWireless infrastructure transceiversRadar/mil-aero sub systemsTest equipment

The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to-digital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The AD9640 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly turn down the system gain to avoid an overrange condition.The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.The ADC output data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.The AD9640 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.Product HighlightsIntegrated dual 14-bit, 80/105/125/150 MSPS ADC.Fast overrange detect and signal monitor with serial output.Signal monitor block with dedicated serial output mode.Proprietary differential input that maintains excellent SNR performance for input frequencies up to 450 MHz.Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.A standard serial port interface that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode.Pin compatibility with theAD9627,AD9627-11, and theAD9600for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits.ApplicationsCommunicationsDiversity radio systemsMultimode digital receiversGSM, EDGE, WCDMA, LTE,CDMA2000, WiMAX, TD-SCDMAI/Q demodulation systemsSmart antenna systemsGeneral-purpose software radiosBroadband data applications

The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital converter (ADC) with a high speed serial output interface. The AD9641 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired. The JESD204A high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth, differential sample-and-hold, analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases the design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data is routed directly to the JESD204A serial output port. This output is at CML voltage levels. A CMOS or LVDS synchronization input (DSYNC) is provided.The flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9641 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONSCommunicationsDiversity radio systemsMultimode digital receivers (3G and 4G)GSM, EDGE, W-CDMA, LTE,CDMA2000, WiMAX, TD-SCDMASmart antenna systemsGeneral-purpose software radiosBroadband data applicationsUltrasound equipmentPRODUCT HIGHLIGHTSAn on-chip PLL allows users to provide a single ADC sampling clock. The PLL multiplies the ADC sampling clock to produce the corresponding JESD204A data rate clock.The configurable JESD204A output block coded data rate supports up to 1.6 Gbps.A proprietary differential input maintains excellent SNR performance for input frequencies up to 250 MHz.Operation is from a single 1.8 V power supply.The standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), controlling the clock DCS, power-down, test modes, voltage reference mode, and serial output configuration.

The AD9642 is a 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9642 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.The ADC output data is routed directly to the external 14-bit LVDS output port.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.The AD9642 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.APPLICATIONSCommunicationsDiversity radio systemsMultimode digital receivers (3G)TD-SCDMA, WiMax, WCDMA,CDMA2000, GSM, EDGE, LTEI/Q demodulation systemsSmart antenna systemsGeneral-purpose software radiosUltrasound equipmentBroadband data applicationsPRODUCT HIGHLIGHTSIntegrated 14-bit, 170 MSPS/210 MSPS/250 MSPS ADC.Operation from a single 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs.Proprietary differential input maintains excellent SNR performance for input frequencies of up to 350 MHz.3-pin, 1.8 V SPI port for register programming and readback.Pin compatibility with theAD9634, allowing a simple migration from 14 bits to 12 bits, and with theAD6672.

The AD9643 is a dual, 14-bit analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9643 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.The ADC output data is routed directly to the external, 14-bit, LVDS output port and formatted as either interleaved or channel multiplexed.Flexible power-down options allow significant power savings, when desired.Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.The AD9643 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.Product HighlightsIntegrated dual, 14-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.Operation from a single 1.8 V supply and a separate digital output driver supply accommodating LVDS outputs.Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.SYNC input allows synchronization of multiple devices.3-pin, 1.8 V SPI port for register programming and register readback.Pin compatibility with theAD9613, allowing a simple migration down from 14 bits to 12 bits. This part is also pin compatible with theAD6649and theAD6643.ApplicationsCommunicationsDiversity radio systemsMultimode digital receivers (3G)TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTEI/Q demodulation systemsSmart antenna systemsGeneral-purpose software radiosUltrasound equipmentBroadband data applications