AD9680 Series

14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

Catalog

14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

Part	Data Interface	Supplier Device Package	Sampling Rate (Per Second)	Reference Type	Number of A/D Converters	Features	Package / Case	Operating Temperature [Max]	Operating Temperature [Min]	Architecture	Mounting Type	Number of Inputs	Configuration	Ratio - S/H:ADC	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Input Type	Number of Bits	Input Range	Utilized IC / Part	Contents	Power (Typ) @ Conditions	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Supplied Contents
Analog Devices AD9680BCPZRL7-1250	JESD204B	64-LFCSP (9x9)	1.25 G	External Internal	2	Simultaneous Sampling	64-WFQFN Exposed Pad CSP	85 °C	-40 °C	Pipelined	Surface Mount	2	S/H-ADC	1:1	1.28 V	1.22 V	Differential	14
Analog Devices AD9680BCPZRL7-500	JESD204B	64-LFCSP (9x9)	500 M	External Internal	2	Simultaneous Sampling	64-WFQFN Exposed Pad CSP	85 °C	-40 °C	Pipelined	Surface Mount	2	S/H-ADC	1:1	1.28 V	1.22 V	Differential	14
Analog Devices AD9680BCPZRL7-1000	JESD204B	64-LFCSP (9x9)	1 G	External Internal	2	Simultaneous Sampling	64-WFQFN Exposed Pad CSP	85 °C	-40 °C	Pipelined	Surface Mount	2	S/H-ADC	1:1	1.28 V	1.22 V	Differential	14
Analog Devices AD9680-LF1000EBZ	JESD204B Serial		1 G		2													14	1.7 Vpp	AD9680	Board(s)	3.3 W
Analog Devices AD9680-LF820EBZ	JESD204B Serial		820 M		2													14	1.7 Vpp	AD9680	Board(s)	2.9 W
Analog Devices AD9680BCPZRL7-820	JESD204B	64-LFCSP (9x9)	820 M	External Internal	2	Simultaneous Sampling	64-WFQFN Exposed Pad CSP	85 °C	-40 °C	Pipelined	Surface Mount	2	S/H-ADC	1:1	1.28 V	1.22 V	Differential	14
Analog Devices AD9680BCPZ-820	SPI	64-LFCSP (9x9)	820 M	Internal	2		64-WFQFN Exposed Pad CSP	85 °C	-40 °C	Pipelined	Surface Mount	2	ADC	1:1	3.3 V	1.8 V	Differential	14					1.8 V	3.3 V
Analog Devices AD9680BCPZ-500	JESD204B	64-LFCSP (9x9)	500 M	Internal	2		64-WFQFN Exposed Pad CSP	85 °C	-40 °C	Pipelined	Surface Mount	2	ADC		1.28 V 3.4 V	1.22 V 1.7 V	Differential	14					1.22 V 2.44 V 3.2 V	1.28 V 2.56 V 3.4 V
Analog Devices AD9680-500EBZ	JESD204B Serial		500 M		2													14	1.7 Vpp	AD9680		2.2 W			Board(s)
Analog Devices AD9680-1000EBZ	JESD204B Serial		1 G		2													14	1.7 Vpp	AD9680		3.3 W			Board(s)

Catalog

14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

Key Features

• JESD204B (Subclass 1) coded serial digital outputs

• 1.65 W total power per channel at 1 GSPS (default settings)

• SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz

• SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN= −1.0 dBFS), 60.5 dBFS at 1 GHz (AIN= −1.0 dBFS)

• ENOB = 10.8 bits at 10 MHz

• DNL = ±0.5 LSB

• INL = ±2.5 LSB

• Flexible input range: 1.46 Vp-pto 1.94 Vp-pAD9680-1250: 1.58 Vp-pnominalAD9680-1000 and AD9680-820: 1.70 V p-p nominalAD9680-500: 1.46 Vp-pto 2.06 Vp-p(2.06 Vp-pnominal)

• AD9680-1250: 1.58 Vp-pnominal

• AD9680-1000 and AD9680-820: 1.70 V p-p nominal

• AD9680-500: 1.46 Vp-pto 2.06 Vp-p(2.06 Vp-pnominal)

• Noise density = −154 dBFS/Hz at 1 GSPS

• 1.25 V, 2.5 V, and 3.3 V dc supply operation

• No missing codes

• Internal ADC voltage reference

• Programmable termination impedance400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

• 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential

• 2 GHz usable analog input full power bandwidth

• 95 dB channel isolation/crosstalk

• Amplitude detect bits for efficient AGC implementation

• 2 integrated wideband digital processors per channel12-bit NCO, up to 4 half-band filters

• 12-bit NCO, up to 4 half-band filters

• Differential clock input

• Integer clock divide by 1, 2, 4, or 8

• Flexible JESD204B lane configurations

• Small signal dither

Description

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital down-converters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTSWide full power bandwidth supports IF sampling of signals up to 2 GHz.Buffered inputs with programmable input termination eases filter design and implementation.Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.Programmable fast overrange detection.9 mm × 9 mm, 64-lead LFCSP.APPLICATIONSCommunicationsDiversity multiband, multimode digital receivers3G/4G, TD-SCDMA, W-CDMA, GSM, LTEGeneral-purpose software radiosUltrawideband satellite receiversInstrumentationRadarsSignals intelligence (SIGINT)DOCSIS 3.0 CMTS upstream receive pathsHFC digital reverse path receivers