Analog Devices

The AD9545 supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks, including ITU-G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2.The 10 clock outputs of the AD9545 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.The AD9545 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.Note that throughout the data sheet, multifunction pins, such as SDO/M5, are referred to either by the entire pin name or by a single function of the pin, for example, M5, when only that function is relevant.APPLICATIONSGlobal positioning system (GPS), PTP (IEEE 1588), and synchronous Ethernet (SyncE) jitter cleanup and synchronizationOptical transport networks (OTN), synchronous digital hierarchy (SDH), and macro and small cell base stationsSmall base station clocking, including baseband and radioStratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient controlJESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clockingCable infrastructuresCarrier Ethernet

The AD9550 is a phase-locked loop (PLL) based clock translator designed to address the needs of wireline communication and base station applications. The device employs an integer-N PLL to accommodate the applicable frequency translation requirements. It accepts a single-ended input reference signal at the REF input.The AD9550 is pin programmable, providing a matrix of standard input/output frequency translations from a list of 15 possible input frequencies to a list of 51 possible output frequency pairs (OUT1 and OUT2).The AD9550 output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9550 is implemented in a strictly CMOS process.The AD9550 operates over the extended industrial temperature range of −40°C to +85°C.APPLICATIONSCost effective replacement of high frequency VCXO, OCXO, and SAW resonatorsFlexible frequency translation for wireline applications such as Ethernet, T1/E1, SONET/SDH, GPON, xDSLWireless infrastructureTest and measurement (including handheld devices)

The AD9551 accepts one or two reference input signals to synthe-size one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended and differential operation.Reference conditioning and switchover circuitry internally synchronizes the two references so that if one reference fails, there is virtually no phase perturbation at the output.The AD9551 uses an external crystal and an internal DCXO to provide for holdover operation. If both references fail, the device maintains a steady output signal.The AD9551 provides pin-selectable, preset divider values for standard (and FEC adjusted) network frequencies. The pin-selectable frequencies include any combination of 15 possible input frequencies and 16 possible output frequencies. A SPI interface provides further flexibility by making it possible to program almost any rational input/output frequency ratio.The AD9551 is a clock generator that employs fractional-N-based phase-locked loops (PLL) using sigma-delta (Σ-Δ) modulators (SDMs). The fractional frequency synthesis capability enables the device to meet the frequency and feature requirements for multiservice switch applications. The AD9551 precisely generates a wide range of standard frequencies when using any one of those same standard frequencies as a timing base (reference). The primary challenge of this function is the precise generation of the desired output frequency because even a slight output frequency error can cause problems for downstream clocking circuits in the form of bit or cycle slips. The requirement for exact frequency translation in such applications necessitates the use of a frac-tional-N-based PLL architecture with variable modulus.ApplicationsMultiservice switchesMultiservice routersExact network clock frequency translationGeneral-purpose frequency translation

The AD9552 is a fractional-N phase locked loop (PLL) based clock generator designed specifically to replace high frequency crystal oscillators and resonators. The device employs a sigma-delta (Σ-Δ) modulator (SDM) to accommodate fractional frequency synthesis. The user supplies an input reference signal by connecting a single-ended clock signal directly to the REF pin or by connecting a crystal resonator across the XTAL pins.The AD9552 is pin programmable, providing one of 64 standard output frequencies based on one of eight common input frequencies. The device also has a 3-wire SPI interface, enabling the user to program custom input-to-output frequency ratios.The AD9552 relies on an external capacitor to complete the loop filter of the PLL. The output is compatible with LVPECL, LVDS, or single-ended CMOS logic levels, although the AD9552 is implemented in a strictly CMOS process.The AD9552 is specified to operate over the extended industrial temperature range of −40°C to +85°C.APPLICATIONSCost effective replacement of high frequency VCXO, OCXO, and SAW resonatorsExtremely flexible frequency translation with low jitter for SONET/SDH (including FEC) , 10 Gb Ethernet, Fibre Channel, and DRFI/DOCSISHigh-definition video frequency translationWireless infrastructureTest and measurement (including handheld devices)

The AD9554-1 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554-1 generates an output clock synchronized to up to four external input references. The digital PLLs (DPLLs) allow reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554-1 continuously generates a low jitter output clock even when all reference inputs have failed.The AD9554-1 operates over an industrial temperature range of −40°C to +85°C. The AD9554 is a version of this device with two outputs per PLL. If a single or dual DPLL version of this device is needed, refer to theAD9557orAD9559, respectively.ApplicationsNetwork synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demappingCleanup of reference clock jitterSONET/SDH clocks up to OC-192, including FECStratum 3 holdover, jitter cleanup, and phase transient controlCable infrastructureData communicationsProfessional video