AD6636150 MSPS Wideband (Digital) Receive Signal Processor (RSP) | RF Misc ICs and Modules | 3 | Active | The AD6636 is a (Digital) Receive Signal Processor intended for direct IF sampling or highly sampled baseband radios requiring wide-bandwidth input signals. It has been optimized for the demanding filtering requirements of wideband standards like, CDMA2000, UMTS, and TD-SCDMA. The AD6636 is designed to be used as part of radio system that uses either an IF sampling ADC, or a baseband sampling ADC.The AD6636 has the following signal processing stages: a Frequency Translator, a 5th order Cascaded Integrated Comb filter, two sets of Cascaded Fixed Coefficient Finite Impulse Response (FIR) and Half Band filters, three cascaded programmable coefficient Sum of Product FIR filters, an Interpolating Half Band Filter (LHB) and a digital Automatic Gain Control (AGC) Block. Multiple modes are supported for clocking data into and out of the chip to provide flexibility for interfacing to a wide variety of digitizers. Programming and control is accomplished via serial or microport interfaces.The AD6636 features a fractional clock multiplier that uses the ADC clock to produce a digital down converter master clock up to 200 MHz. This internal phased-locked loop (PLL) allows optimum digital clock rates, regardless of the converter sampling rate, enabling the best possible digital signal decimation and filtering. Three 16-bit parallel output ports accommodate high data rate 3G applications. An on-chip interpolating half band filter can also be used to further increase the output rate while still allowing for very efficient filters. In addition, each channel has a digital AGC for output data scaling. |
AD664Monolithic 12-Bit Quad DAC | Integrated Circuits (ICs) | 26 | Active | The AD664 is four complete 12-bit, voltage-output digital-toanalog converters (DACs) on one monolithic IC chip. Each DAC has a double buffered input latch structure and a data readback function. All DAC read and write operations occur through a single microprocessor-compatible input/output (I/O) port.The I/O port accommodates 4-bit, 8-bit, or 12-bit parallel words allowing simple interfacing with a wide variety of microprocessors. A reset to zero control pin is provided to allow a user to simultaneously reset all DAC outputs to zero, regardless of the contents of the input latch. Any one or all of the DACs may be placed in a transparent mode allowing immediate response by the outputs to the input data.The analog portion of the AD664 consists of four DAC cells, four output amplifiers, a control amplifier, and switches. Each DAC cell is an inverting R-2R type. The output current from each DAC is switched to the on-board application resistors and output amplifier. The output range of each DAC cell is programmed through the digital input/output port and may be set to unipolar (UNI) or bipolar (BIP) range, with a gain of one or two times the reference voltage. All DACs are operated from a single external referenceThe functional completeness of the AD664 results from the combination of the Analog Devices, Inc., BiMOS II process, laser trimmed thin film resistors, and double level metal interconnects. |
| Analog to Digital Converters (ADC) | 1 | Active | |
| Evaluation Boards | 3 | Active | |
| RF Misc ICs and Modules | 1 | Active | The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI.With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6642 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6642 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6642 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6642 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are desired.After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels.The AD6642 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods.Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board-level system testing.The AD6642 is available in a Pb-free/RoHS compliant, 144-ball, 10 mm × 10 mm chip scale package ball grid array (CSP_BGA) and is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONSCommunicationsDiversity radio and smart antenna (MIMO) systemsMultimode digital receivers (3G)WCDMA, LTE, CDMA2000WiMAX, TD-SCDMAI/Q demodulation systemsGeneral-purpose software radiosPRODUCT HIGHLIGHTSTwo ADCs are contained in a small, space-saving, 10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.Pin selectable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of up to 60 MHz at 185 MSPS.LVDS digital output interface configured for low cost FPGA families.120 mW per ADC core power consumption.Operation from a single 1.8 V supply.Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary or twos complement), NSR, power-down, test modes, and voltage reference mode.On-chip integer 1-to-8 input clock divider and multichip sync function to support a wide range of clocking schemes and multichannel subsystems. |
| RF, RFID, Wireless Evaluation Boards | 5 | Active | |
| Analog to Digital Converters (ADC) | 3 | Active | |
AD664514-Bit, 80 MSPS/105 MSPS A/D Converter | Evaluation Boards | 3 | Active | The AD6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible digital outputs. It is the fourth generation in a wideband ADC family, preceded by theAD9042(12-bit, 41 MSPS), theAD6640(12-bit, 65 MSPS, IF sampling), and theAD6644(14-bit, 40 MSPS/65 MSPS).Designed for multichannel, multimode receivers, the AD6645 is part of the Analog Devices, Inc., SoftCell®transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio (SNR) is 74.5 dB through the first Nyquist band.The AD6645 is built on the Analog Devices extra fast complementary bipolar (XFCB) process and uses an innovative, multipass circuit architecture. Units are available in a 52-lead exposed pad (TQFP_EP) package specified from −40°C to +85°C at 80 MSPS and −10°C to +85°C at 105 MSPS.Product HighlightsIF Sampling. The AD6645 maintains outstanding ac performance up to input frequencies of 200 MHz, suitable for multicarrier 3G wideband cellular IF sampling receivers.Pin Compatibility. The ADC has the same footprint and pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC.SFDR Performance and Oversampling. Multitone SFDR performance of 100 dBFS can reduce the requirements of high end RF components.ApplicationsMultichannel, multimode receiversBase station infrastructuresAMPS, IS-136, CDMA, GSM, W-CDMASingle channel digital receiversAntenna array processingCommunications instrumentationRadars, infrared imagingInstrumentation |
| RF Misc ICs and Modules | 2 | Active | The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.The AD6649 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.Flexible power-down options allow significant power savings, when desired.Programming for setup and control is accomplished using a 3-pin SPI-compatible serial interface.The AD6649 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.ApplicationsCommunicationsDiversity radio systemsMultimode digital receivers (3G)TD-SCDMA, WiMax, WCDMA,CDMA2000, GSM, EDGE, LTEGeneral-purpose software radiosBroadband data applicationsProduct HighlightsIntegrated dual, 14-bit, 250 MSPS ADC.Integrated wideband decimation filter and 32-bit complex NCO.Fast overrange and threshold detect.Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz.SYNC input allows synchronization of multiple devices.3-pin, 1.8V SPI port for register programming and register readback. |
AD665212-Bit, 65 MSPS IF to Base Band Diversity Receiver | RF and Wireless | 1 | Active | The AD6652 is a mixed-signal IF to baseband receiver consisting of dual 12-bit MSPS ADCs and a wideband multimode digital downconverter (DDC). The AD6652 is designed to support communications applications where low cost, small size, and versatility are desired. The AD6652 is also suitable for other applications in imaging, medical ultrasound, instrumentation, and test equipment.APPLICATIONSCommunicationsDiversity radio systems Multimode digital receivers:GSM, EDGE, PHS, AMPS, UMTS, WCDMA, CDMA-ONE,IS95, IS136, CDMA2000, IMT-2000I/Q demodulation systemsSmart antenna systemsGeneral-purpose software radiosBroadband data applicationsInstrumentation and test equipmentPRODUCT HIGHLIGHTSIntegrated dual 12-bit 65 MSPS ADC.Integrated wideband digital downconverter (DDC).Proprietary, differential SHA input maintains excellent SNR performance for input frequencies up to 200 MHz.Crossbar-switched digital downconverter input ports.Digital resampling permits noninteger relationships between the ADC clock and the digital output data rate.Energy-saving power-down modes.32-bit NCOs with selectable amplitude and phase dithering for better than −100 dBc spurious performance.CIC filters with user-programmable decimation and interpolation factors.160-tap RAM coefficient filter for each DDC channel.Dual 16-bit parallel output ports and dual 8-bit link ports.8-bit microport for register programming, register read-back, and coefficient memory programming. |
